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Инструкция обслуживания Cypress CY7C64113C

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Summary
  • Cypress CY7C64113C - page 1

    Full-S peed USB (12-Mbp s) Function CY7C64013C CY7C641 13C Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-08001 Rev . *B Revised March 3, 2006 Full-Speed USB (12-Mbps) Function [+] Feedback ...

  • Cypress CY7C64113C - page 2

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 2 of 51 TABLE OF CONTENTS 1.0 FEATURES ..................................................... ........................................... .................. .....................6 2.0 FUNCTIONAL OVERVIEW ....................................... .......................................... ...... ...

  • Cypress CY7C64113C - page 3

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 3 of 51 TABLE OF CONTENTS 16.6 DAC Interrupt .......................................................................... .................................. .............. 31 16.7 GPIO/HAPI Interrupt ............................................................... .............................. ...

  • Cypress CY7C64113C - page 4

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 4 of 51 LIST OF FIGURES Figure 6-1. Clock Oscillator On-Chip Circuit ............................................................... .................... ....... 17 Figure 7-1. Watchdog Reset (WDR) ........................................................................... .................. ...

  • Cypress CY7C64113C - page 5

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 5 of 51 LIST OF TABLES Table 4-1. Pin Assignments ............................................. ....................................................... ........ ...... 10 Table 4-2. I/O Register Summary ......................................................... ............................... ...

  • Cypress CY7C64113C - page 6

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 6 of 51 1.0 Features • Full-speed USB Mic rocontroller • 8-bit USB Optimize d Microcontroller — Harvard architecture — 6-MHz external clock so urce — 1 2-MHz internal CPU clock — 4 8-MHz internal clock • Internal memory — 256 bytes of RAM — 8 KB of PROM (CY7C64013C, CY7C641 ...

  • Cypress CY7C64113C - page 7

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 7 of 51 2.0 Functional Overview The CY7C64013C and CY7C641 13 C are 8-bit One Time Programmab le microcontrollers that are d esigned for full-speed USB applications. The i nstruction set has been op timized specifically for USB operations, alth ough the microcontrollers can be used for a var ...

  • Cypress CY7C64113C - page 8

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 8 of 51 Logic Block Diagram Interrupt Controller PROM 12-bit Timer Reset W atchdog Tim er Power-On SCLK I 2 C GPIO PORT 1 GPIO PORT 0 P0[7:0] P1[2:0] P1[7:3] SDATA 8-bit Bus 6-MHz crystal RAM USB SIE USB Transceiver D+[0] D–[0] Upstream USB Port P3[2:0] DAC PORT DAC[0] DAC[2] High Current ...

  • Cypress CY7C64113C - page 9

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 9 of 51 3.0 Pin Configurations 1 2 3 4 5 6 7 9 11 12 13 14 15 16 18 17 XTALIN 10 8 19 20 31 30 29 33 32 35 34 37 36 39 38 41 40 43 42 45 44 46 48 47 21 22 23 24 25 27 26 28 V CC P1[1] P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] V REF P1[3] P1[5] P1[7] P3[1] D+[0] D–[0] P3[3] GND P3[5] P3[7] P2[1] ...

  • Cypress CY7C64113C - page 10

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 10 of 51 4.0 Product Summary T ables 4.1 Pin Assign ments 4.2 I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instruct ions. IORD re ads data from the selected port into the accu mulator . IOWR performs the reverse; it writes dat a from the ...

  • Cypress CY7C64113C - page 11

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 1 1 of 51 GPIO Configuration 0x08 R/W GPIO Port Configurations 20 HAPI and I 2 C Configuration 0x09 R/W HAPI Width and I 2 C Position Configuration 24 USB Device Address A 0x10 R/W USB Device Address A 34 EP A0 Counter Register 0x1 1 R/W USB Address A, Endpoint 0 Counter 35 EP A0 Mode Regist ...

  • Cypress CY7C64113C - page 12

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 12 of 51 4.3 Instructi on Set Summary Refer to th e CY ASM Assembler User ’s Guide for more det ails. T ab le 4-3. Instruction Set Summary MNEMONIC operand opcode cycles MNEMON IC operand opcode cycles HAL T 00 7 NOP 20 4 ADD A,expr data 01 4 INC A acc 21 4 ADD A,[expr] direct 02 6 INC X x ...

  • Cypress CY7C64113C - page 13

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 13 of 51 5.0 Programming Model 5.1 14-Bit Program Counte r (PC) The 14-bit program counter (PC) a llows access to up to 8 KB of PROM availabl e with the CY7C64x13 C architecture. The top 32 bytes of the ROM in the 8 Kb part are reserved for testing purpose s. The program counter is cleared d ...

  • Cypress CY7C64113C - page 14

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 14 of 51 5.1.1 Program Memory Orga nization after reset Address 14-bit PC 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128-µs timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008 USB address A endpoint 0 interrupt vector 0x0 ...

  • Cypress CY7C64113C - page 15

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 15 of 51 5.2 8-Bit Accumulator (A) The accumulator is the general-purpose register for the microcontroller. 5.3 8-Bit T e mporary Regist er (X) The “X” register is available to the firmware for temporary st orage of intermediate results. The microcontroller can perfo rm in dexed operatio ...

  • Cypress CY7C64113C - page 16

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 16 of 51 5.5 8-Bit Data S tack Pointer (DSP) The data stack pointer (DSP) supports PUSH and POP i nstruct ions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP , then writes data to the memo ry location addressed by the DSP . A POP i nstruction reads d ...

  • Cypress CY7C64113C - page 17

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 17 of 51 6.0 Clocking The XT ALIN and XT ALOUT are the clock pins to the microcontroller . The user can connect an external oscillator or a crystal to these pins. When using an externa l crystal, keep PCB traces betw een the ch ip leads and crystal as short as possible (less than 2 cm). A 6- ...

  • Cypress CY7C64113C - page 18

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 18 of 51 The USB transmitter is disabled by a Watchdog Reset because th e USB De vice Address Register is clea red (see Section 18.1). Otherwise, the USB Controller would respond to all address 0 transactio ns. It is possible for the WDR bit of the Processor S tatus and Control Register (0xF ...

  • Cypress CY7C64113C - page 19

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 19 of 51 9.0 General-Purpose I/O (GPIO) Port s There are up to 32 GPIO pins (P0[7:0], P1 [7:0], P2[7:0], and P3[7:0]) for the hardw are interface. Th e number of GPIO pins changes based on the package type of the chip. Each port can be configured as inputs with inte rn al pull-ups, open drai ...

  • Cypress CY7C64113C - page 20

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 20 of 51 Port 3 Dat a ADDRESS 0x03 S pecial care shoul d be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a p ort bit th at is not bonded on a particular package, must not be left floating when the device enters the suspe nd state. If a GPIO data ...

  • Cypress CY7C64113C - page 21

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 21 of 51 Q1, Q2, and Q3 discussed below are the transistors referenced in Figu re 9-1 . The available GPIO drive strength are: • Output LOW Mode: The pin’s Dat a Register is set to ‘0’ Writing ‘0’ to the pin’s Data Register puts the pin in output L OW mode, regardless of the co ...

  • Cypress CY7C64113C - page 22

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 22 of 51 The amount of sink current for the DAC I/O pin is progra mmable ov er 16 values based on the co ntents of the DAC Isink Register for that output pin. DAC[1:0] are high-current outp uts that are programmable from 3.2 mA to 16 mA (typic al). DAC[7:2] are low- current outputs, programm ...

  • Cypress CY7C64113C - page 23

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 23 of 51 Bit [4..0]: Isin k [x] (x= 0..4) Writing all ‘0’s to the Isink register caus es 1/5 of the max current to flow through the DAC I/O pin. Writing all ‘1’s to the Isink register provides the maximum current flow thro ugh the pin. The o ther 14 st ates of the DAC sink cu rrent a ...

  • Cypress CY7C64113C - page 24

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 24 of 51 Tim er M SB ADDRESS 0x25 Bit [3:0]: Timer higher nibble Bit [7:4]: Reserved 12.0 I 2 C and HAPI Configuration Regi ster Internal hardware supports communication with exte rnal devices through two inte rfaces: a two-wire I 2 C-compatible interface, and a HAPI for 1, 2, or 3 byte tran ...

  • Cypress CY7C64113C - page 25

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 25 of 51 13.0 I 2 C-comp atible Controller The I 2 C-compatible block provides a versatile two-wire communication with external devices, supporting master , slave, and multi- master modes of operation. The I 2 C-compatible block functions by handling the low-l evel signaling in hardware, a n ...

  • Cypress CY7C64113C - page 26

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 26 of 51 Bit 7 : MSTR Mode Setting this bit to 1 causes the I 2 C-co mpatible block to initiate a master mode transaction b y sending a start bit and transmitting the first data byte from the data register (this ty pically holds the target address and R/W bit). Sub sequent bytes are initiate ...

  • Cypress CY7C64113C - page 27

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 27 of 51 to the data register before setting the Continue bit. T o preven t fa lse ARB Lost signals, th e Restart bit is cleared by hardware during the restart sequence. Bit 1 : Receive Stop This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive S to ...

  • Cypress CY7C64113C - page 28

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 28 of 51 15.0 Processor S t atus and Control Register Processor St atus and Control ADDRESS 0xFF Bit 0: Run This bit is manipulated by the HAL T inst ruction. When Halt is executed , all the bi ts of the Processo r S tatus and Con trol Register are cleared to 0 . Since the run bi t is cleare ...

  • Cypress CY7C64113C - page 29

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 29 of 51 16.0 Interrupt s Interrupts are generated by the GPIO/D AC pins, the internal timers, I 2 C-compatible interface or HAPI op eration, or on various USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Poi nt Interrupt Ena ble Reg ...

  • Cypress CY7C64113C - page 30

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 30 of 51 The interrupt controller con tains a separate flip-flop for each interrupt. See F igure 16-3 for the logic block diagram of the inte rrupt controller . When an interrupt is generated, it is first registered as a pend ing interru pt. It stays pending until it is service d or a reset ...

  • Cypress CY7C64113C - page 31

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 31 of 51 16.2 Interrupt Latency Interrupt latency can be calculated from the following equation: Interrupt latency = (Number of clock cycles remaining in the current inst ruction) + (10 clock cycles for the CALL instruction) + (5 clock cycles for the JMP instruction) For example, if a 5 cloc ...

  • Cypress CY7C64113C - page 32

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 32 of 51 16.7 GPIO/HAPI Interrupt Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as part of the GPIO configuration. All of the GPIO pins share a single interrupt vector , which means the firmware needs to rea d th e GP ...

  • Cypress CY7C64113C - page 33

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 33 of 51 5. In ma ster receive mode, af ter the master receives a byte of data: Firmware should read the data and set the ACK and Continue/Busy bits appropriately for the next byte. Clearing the MSTR MODE bit at the same time causes the master state machine to issue a stop signal to the I 2 ...

  • Cypress CY7C64113C - page 34

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 34 of 51 USB St atus and Control ADDRESS 0x1F Bits [2..0] : Control Action Set to control action as per T able 17-1 .The three co ntrol bits allow the upstream port to be driven manu ally by firmware. For normal USB operation, all of these bits must be cleared. T able 17-1 shows how the con ...

  • Cypress CY7C64113C - page 35

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 35 of 51 Bits[6..0] :Device Address Firmware writes this bits during the USB enumeration process to the non-zero address assigned by the USB host. Bit 7 :Device Address Enable Must be set by firmware before the SIE can resp ond to USB traf fic to the Device Address. Bit 7 (Device Address Ena ...

  • Cypress CY7C64113C - page 36

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 36 of 51 Bit 6: End point 0 IN Received 1= T oken received is an IN token. 0= T oken received is not an IN token. This bit is set by the SIE to report the type o f token received by the correspondin g device address is an IN token. The bit mu st be cleared by firmware as part of the USB proc ...

  • Cypress CY7C64113C - page 37

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 37 of 51 Bits [5..0] : Byte Count These counter bits indicate the number of data bytes in a tra n saction. For IN transactions, firmware lo ads the count with the numbe r of bytes to be transmit ted to the h ost from th e end point FIFO. V ali d values are 0 to 32, inclusive. For OUT or SETU ...

  • Cypress CY7C64113C - page 38

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 38 of 51 A C K 1. IN T oken H O S T D E V I C E S Y N C IN A D D R C R C 5 E N D P S Y N C D A T A 1/0 C R C 16 S Y N C Data Token Packet Data Packet Hand Shake Packet UPDATE Host To Device Device To Host Host To Device S Y N C IN A D D R C R C 5 E N D P Token Packet Host To Device S Y N C D ...

  • Cypress CY7C64113C - page 39

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 39 of 51 19.0 USB Mode T ables Mode This lists the mnemonic given to the different modes that can be set in the Endpoint Mode Register by writing to the lo wer nibb le (bits 0..3). The bit settings for different modes are covered in the column ma rked “Mode Bits”. The S tatus IN and S ta ...

  • Cypress CY7C64113C - page 40

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 40 of 51 An “Accept” in any of the columns means that the device will respond with an ACK to a valid SETUP transaction tot he host. Comments Some Mode Bits are automatically chan ged by the SIE in respons e to certain USB transactions. For example, if the Mo de Bits [3:0] are set to &apo ...

  • Cypress CY7C64113C - page 41

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 41 of 51 the firmware recognizes the changes that the SIE might have made during the previo us transaction . Note that the setup bit of the mode register is NOT locked. This mean s that before writing to th e mode register , firmware must first read the register to make sure that the setup b ...

  • Cypress CY7C64113C - page 42

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 42 of 51 1 1 1 0 Out !=2 UC valid updates 1 updates UC UC 1 UC 0 0 1 1 St all yes 1 1 1 0 Out > 10 UC x UC UC UC UC UC UC UC NoChange ignore no 1 1 1 0 Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no 1 1 1 0 In x UC x UC UC UC UC 1 UC UC NoChange NAK yes S tatu s Out/extra In 0 0 ...

  • Cypress CY7C64113C - page 43

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 43 of 51 20.0 Register Summary Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write/ Both/- Default/ Reset GPIO CONFIGURA TION PO RTS 0, 1, 2 AND 3 0x00 Port 0 Dat a P0.7 P0.6 P0.5 P0.4 P0.3 P 0.2 P0.1 P0.0 BBBBBBBB 11111 111 0x01 Port 1 Dat a P1.7 P1.6 P1.5 P1.4 ...

  • Cypress CY7C64113C - page 44

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 44 of 51 Note: B: Read and W rite W: Wri te R: Read 21.0 Sample Schematic RESERVE D 0x48 Reserved Reserved Reserved Reserved Reserved Re s erved Reserved Reserved Rese rved Reserved 00000000 0x49 Reserved Reserved Reserved Reserved Reserved Re s erved Reserved Reserved Rese rved Reserved 000 ...

  • Cypress CY7C64113C - page 45

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 45 of 51 22.0 Absolute Maximum Ratings S torage T emperature ........... .............. ................ .......................... .............. .............. ............ ............. .............. .... –65°C to +150°C Ambient T emperature with Power Applied ................... ... ...

  • Cypress CY7C64113C - page 46

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 46 of 51 DAC Interface R up DAC Pull-up Resistance (typical 14 k Ω) 8.0 24.0 k Ω I sink0(0) DAC [7:2] Sink current (0) V out = 2.0V DC 0.1 0.3 mA I sink0(F) DAC[7:2] Sink current (F) V out = 2.0V DC 0.5 1.5 mA I sink1(0) DAC [1:0] Sink current (0) V ou t = 2.0V DC 1.6 4 .8 mA I sink1(F) ...

  • Cypress CY7C64113C - page 47

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 47 of 51 Figure 24-1. Clock Timing Figure 24-2. USB Data Signal T iming Figure 24-3. HAPI Read by External Interfac e from USB Microcontroller CLOCK t CYC t CL t CH 90% 10% 90% 10% D − D + t r t r OE (P2.5, input) DATA (output) STB (P2.4, inp ut) DReadyPin (P2.3, output) Internal Write Int ...

  • Cypress CY7C64113C - page 48

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 48 of 51 25.0 Ordering Information Ordering Code PR OM Size Packag e T ype Operating Range CY7C64013C-SXC 8 KB 28-Pin (300-Mil) SOIC Commercial CY7C64013C-PXC 8 KB 28-Pin (300-Mil) PDIP Commercial CY7C64013C-SXCT 8 KB 28-Pin (300-Mil) SOIC - T ape Reel Comme rcial CY7C641 13C-PVXC 8 KB 48-Pi ...

  • Cypress CY7C64113C - page 49

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 49 of 51 26.0 Package Diagrams 48-Lead Shrunk Small Ou tline Package 51-85061-*C DIMENSIONS IN INCHES [MM] MIN. MAX. SEATING PLANE 0.260[6.60] 0.295[7.49] 0.090[2.28] 0.110[2.79] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 0.015[0.38] 0.060[1.52] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012 ...

  • Cypress CY7C64113C - page 50

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 50 of 51 © Cypress Semi conductor Corporati on, 2006. The info rmation conta ined herein is su bject to change without notice. Cypress Semic onduct or Corporation assumes no responsibility for th e use of any circuitry o ther than circuitr y embodied in a Cypress product. Nor does it convey ...

  • Cypress CY7C64113C - page 51

    CY7C64013C CY7C641 13C Document #: 38-08001 Rev . *B Page 51 of 51 Document History Page Document Title: CY7C64013C, CY7C641 13C Full-Speed USB (12 Mbp s) Function Document Number: 38-08001 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 109962 12/16/01 SZV Change from Spec number: 38-00626 to 38-08001 *A 129715 02/05 /04 MON Adde ...

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