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Cypress CY7C1217H - page 1
CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAM Cypress Semiconductor Corpora tion • 198 Champion Cou rt • San Jose , CA 95134-1 709 • 408-943-2 600 Document #: 38-05670 Rev . *B Revised July 6, 2006 Features • 32K x 36 common I/O • 3.3V core power supply (V DD ) • 2.5V/3.3V I/O power supply (V DDQ ) • Fast clock-to-output times ? ...
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Cypress CY7C1217H - page 2
CY7C1217H Document #: 38-05670 Rev . *B Page 2 of 16 Logic Block Diagram ADDRESS REGISTER BURST COUNTER AND LOGIC CLR Q1 Q0 ENABLE REGISTER SENSE AMPS OUTPUT BUFFERS INPUT REGISTERS MEMORY ARRAY MODE A [1:0] ZZ DQ s DQP A DQP B DQP C DQP D A 0, A1, A ADV CLK ADSP ADSC BW D BW C BW B BW A BWE CE1 CE2 CE3 OE GW SLEEP CONTROL DQ A , DQP A BYTE WRITE R ...
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Cypress CY7C1217H - page 3
CY7C1217H Document #: 38-05670 Rev . *B Page 3 of 16 Pin Configuration 100-Pin TQFP A A A A A 1 A 0 NC/72M NC/36M V SS V DD NC/9M A A A A A NC/4M DQP B DQ B V DDQ V SSQ DQ B DQ B DQ B DQ B V SSQ V DDQ DQ B DQ B V SS NC V DD DQ A DQ A V DDQ V SSQ DQ A DQ A DQ A DQ A V SSQ V DDQ DQ A DQ A DQP A DQP C DQ C DQ C V DDQ V SSQ DQ C DQ C DQ C DQ C V SSQ V ...
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Cypress CY7C1217H - page 4
CY7C1217H Document #: 38-05670 Rev . *B Page 4 of 16 Pin Descriptions Name I/O Description A0, A1, A Input- Synchronous Address Inputs used to select one of the 32K address location s. Sampled at the rising edge of the CL K if ADSP or ADSC is active LOW , and CE 1 , CE 2 , and CE 3 are sampled active. A [1:0] feed the 2-bit counter . BW A , BW B BW ...
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Cypress CY7C1217H - page 5
CY7C1217H Document #: 38-05670 Rev . *B Page 5 of 16 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge o f the clock. Maximum access delay from the clock rise (t CDV ) is 6.5 ns (133-MHz device). The CY7C1217H supports secondary cache in systems utilizing either a linear or interleaved burst sequ ...
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Cypress CY7C1217H - page 6
CY7C1217H Document #: 38-05670 Rev . *B Page 6 of 16 ZZ Mode Electrical Characteristics Parameter Description T est Conditions Min. Max. U nit I DDZZ Sleep mode standby current ZZ > V DD – 0.2V 40 mA t ZZS Device operation to ZZ ZZ > V DD – 0.2V 2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V 2t CY C ns t ZZI ZZ Active to sleep current Th ...
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Cypress CY7C1217H - page 7
CY7C1217H Document #: 38-05670 Rev . *B Page 7 of 16 T ruth T able for Read/W rite [2, 3] Function GW BWE BW D BW C BW B BW A R e a d H HXXXX R e a d H L HHHH Write Byte (A, DQP A ) H L HHH L Write Byte (B, DQP B )H L H H L H Write Bytes (B, A, DQP A , DQP B )H L H H L L Write Byte (C, DQP C ) HLHLH H Write Bytes (C, A, DQP C , DQP A ) HLHLHL Write ...
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Cypress CY7C1217H - page 8
CY7C1217H Document #: 38-05670 Rev . *B Page 8 of 16 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) S torage T emperature ............. ... ... ... ... ....... –65 ° C to + 150 ° C Ambient T e mperature with Power Applied ........ ... ... ... ........... ... ... ... ....... –55 ° C to + 125 ...
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Cypress CY7C1217H - page 9
CY7C1217H Document #: 38-05670 Rev . *B Page 9 of 16 Cap acit ance [9] Parameter Description T est Co nditions 100 TQFP Max. Unit C IN Input Capacit ance T A = 25 ° C, f = 1 MHz, V DD = 3.3V . V DDQ = 2.5V 5p F C CLK Clock Input Capacit ance 5 pF C I/O Input/Output Capacit ance 5 pF Thermal Resist ance [9] Parameter Descrip tio n T est Co nditions ...
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Cypress CY7C1217H - page 10
CY7C1217H Document #: 38-05670 Rev . *B Page 10 of 16 Switching Characteristics Over the Operating Range [10, 1 1] Parameter Description 133 MHz 100 MHz Unit Min. Max. Min. Max. t POWER V DD (T ypical) to the First Access [12] 11 m s Clock t CYC Clock Cycle T ime 7.5 10 ns t CH Clock HIGH 2.5 4.0 ns t CL Clock LOW 2.5 4.0 ns Output Times t CDV Dat ...
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Cypress CY7C1217H - page 11
CY7C1217H Document #: 38-05670 Rev . *B Page 1 1 of 16 Timing Diagrams Read Cycle Timing [16] Note: 16. On this diagram, when CE is L OW, CE 1 is LOW , CE 2 is HIGH and CE 3 is LOW. When CE is HIGH, CE 1 is HIGH or CE 2 is LOW or CE 3 is HIGH. t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES Data Out (Q) High-Z t CLZ t DOH t CDV t O ...
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Cypress CY7C1217H - page 12
CY7C1217H Document #: 38-05670 Rev . *B Page 12 of 16 Write Cycle T iming [16, 17] Note: 17. Full width Write can be initiated b y either GW LOW; or by GW HIGH, BWE LOW and BW [A:D] LOW. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A1 t CEH t CES High-Z BURST READ BURST WRITE D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D( ...
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Cypress CY7C1217H - page 13
CY7C1217H Document #: 38-05670 Rev . *B Page 13 of 16 Read/Write T iming [16, 18, 19] Notes: 18. The data bus (Q) remains in High-Z following a Write cycle unless an ADS P , ADSC , or ADV cycle is performed. 19. GW is HIGH. Timing Diagrams (continued) t CYC t CL CLK t ADH t ADS ADDRESS t CH t AH t AS A2 t CEH t CES Single WRITE D(A3) A3 A4 BURST RE ...
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Cypress CY7C1217H - page 14
CY7C1217H Document #: 38-05670 Rev . *B Page 14 of 16 ZZ Mode T iming [20, 21] Notes: 20. Device must be deselected when ente ring ZZ mode. See Cycle Descr iptions t ab le for all possible signal conditi ons to deselect the device. 21. DQs are in High-Z when exiting ZZ sleep mode. Timing Diagrams (continued) t ZZ I SUPPLY CLK ZZ t ZZREC A LL INPUTS ...
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Cypress CY7C1217H - page 15
CY7C1217H Document #: 38-05670 Rev . *B Page 15 of 16 © Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is su bject to change wi t hou t n oti ce. C ypr ess S em ic onduct or Corporation assumes no resp onsibility f or the u se of any circuitry o ther than circui try embodied i n a Cypress prod uct. Nor do ...
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Cypress CY7C1217H - page 16
CY7C1217H Document #: 38-05670 Rev . *B Page 16 of 16 Document History Page Document Title: CY7C1217H 1-Mbit (32K x 36) Flow-Through Sync SRAM Document Number: 38 -05670 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 345879 See ECN PCI New Data Sheet *A 430677 See ECN NXR Changed ad dress of Cypress Semi conductor Corporation on ...
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