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Xilinx ChipScope PLB46 IBA v1.00a - page 1
DS619 April 7, 2009 www .xilinx.com 1 Product Specification © 2009 Xilinx, Inc. X ilinx, Inc. XILINX, the Xilinx lo go, V i rtex, Spartan, ISE and other designate d brands included herein are trademarks of Xilinx in th e United States and other countries. All other trad emarks are the property of their re specti ve owners. Intr oduction The ChipSc ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 2
2 www .xilinx.com DS619 April 7, 2009 Product Specification ChipScope PLB46 IBA I/O Signals T able 1: IBA_PLBv46 Pin Descriptions Port MU Signal Name Interface I/O Description P1 CONTROL ICON I/O Icon control bus IO P2 PLB_Clk System I System Clock P3 MU_1C iba_trigin_in GENERIC I Generic T rigger Inputs P4 iba_trig_out GENERIC O IBA T rigger Outpu ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 3
DS619 April 7, 2009 www .xilinx.com 3 Product Specification P32 MU_2B PLB_masterID[0: C_PLBV46_MID_WIDTH-1] Slave I PLB current ma ster identifier P33 MU_2B PLB_BE[0: C_PLBV46_DWIDTH/8-1] Slave I PLB byte enable s P34 MU_2C PLB_T Attribute[0:15] Sl ave I PLB Transfer Attribute Address P35 MU_3A PLB_ABus[0:31] Slave I PLB address bus, lower 32 bits ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 4
4 www .xilinx.com DS619 April 7, 2009 Product Specification P54 MU_9 Sl_MWrErr[0: C_PLBV46_NUM_SLA VES *C_PLBV46_NUM_MASTERS-1] Slave I Slave write error indicator PLB Arbitr ation Signals P55 MU_10 M_request[0: C_PLBV46_NUM_MASTERS-1] Master I Master bus request P56 MU_10 M_priority[0: C_PLBV46_NUM_MASTERS*2-1] Master I Master bus request priority ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 5
DS619 April 7, 2009 www .xilinx.com 5 Product Specification The IBA_PLBv46 por ts listed in Ta b l e 1 connect to the PLBv46 bus. The core divides related ports into 13 match unit groups (MUs) as shown i n the second column of the table. Each m atch unit group can conn ect to a trigger port of the IBA. Certain match unit groups, such as MU_1, are f ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 6
6 www .xilinx.com DS619 April 7, 2009 Product Specification When these match units are enabled, all slaves or master s are enabled. Y ou canno t individually enable a particular master . The match units 7, 8, and 9 are slave side signals for BUSY , READ, and WRITE error controls going to the mas- ter . These units are broken out individually becaus ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 7
DS619 April 7, 2009 www .xilinx.com 7 Product Specification G13 Enable T rigger Out C_ENAB LE_TRIGGER_OUT 1,0 0 Integer T rigger In, PLB Reset, and PLB Erro r S tatus G14 Use system rese t and error status signals C_USE_MU_1A_RST_ERR_ ST A T 1,0 1 Integer G15 Use master error status signals C_USE_MU_1B_MSTR_RST_ ERR_ST A T 1,0 0 Integer G16 Use iba ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 8
8 www .xilinx.com DS619 April 7, 2009 Product Specification G32 1=Enable storing MU 3 signals in the data sample storage buffer . 0=Disable C_USE_MU_3A_ABUS or must C_USE_MU_3B_UABUS be 1 in order to store. C_MU_3_EN_STORE_ADDR 0,1 1 Integer PLB Data G33 Use PLB_wrDBus C_USE_ MU_4_WR_DBUS 1,0 0 Integer G34 0=basic, 1=basic w/ edges, 2=extended, 3= ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 9
DS619 April 7, 2009 www .xilinx.com 9 Product Specification G46 1=Enable storing MU 6 signals in the data sample storage buffer . 0=Disable C_USE_MU_6A_SL V_CTL or C_USE_MU_6B_SL V_SZ_W ADD R must be 1 in order to store. C_MU_6_EN_STORE_SL V_ CTL_BUS 0,1 1 Integer Slave Busy S tatus G47 USE SI _MBusy signal C_USE_MU_7_SL V_BSY 1,0 0 Integer G48 0=b ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 10
10 www .xilinx.com DS619 April 7, 2009 Product Specification Ta b l e 2 lists the IBA PLBv46 parameterized feat ures, which c ontrol the ports attached to the IBA trigger and stor- age units. They also are used to co nfigure the storage and match unit op tions available for each trigger port. The IBA ports are subdi vided into logical group s call ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 11
DS619 April 7, 2009 www .xilinx.com 11 Product Specification Every match unit group has a match type and mat ch counter width parameter . The match unit type describes the type of compare operation that can be done on a match unit. Th e valid values for this type are defined for each match unit. For example, C_MU_1_TYPE only sup ports basic and bas ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 12
12 www .xilinx.com DS619 April 7, 2009 Product Specification Design Implementation The ChipScope PLB IBA desi gn is implemented in a T cl script. Wh en the EDK Platgen tool is run, thi s T cl script is called and it internally calls the ChipScope Pro Core generator in command line mode providin g a generated argument (.ar g) file to create a custom ...
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Xilinx ChipScope PLB46 IBA v1.00a - page 13
DS619 April 7, 2009 www .xilinx.com 13 Product Specification Revision History Notice of Disclaimer Xilinx is providing this design, code, or inform ation (collectively , the “Information”) to you “ AS-IS ” with no warranty of any kind, express or implied. Xilinx makes no re presentation that the Information, or any particular implementation ...
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