English dropdown-ico

Manual Maxim DS21Q55

248 pages 3.19 mb
Download

Go to site of 248

Summary
  • Maxim DS21Q55 - page 1

    Product Preview DS21Q55 Note : This Product Preview contains preliminary information and is subject to change without notice. Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about d ...

  • Maxim DS21Q55 - page 2

    Product Preview DS21Q55 2 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 1. DESCRIPTION The DS21Q55 is a quad MCM devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line inter face unit (LIU), framer, H ...

  • Maxim DS21Q55 - page 3

    Product Preview DS21Q55 3 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . The device fully meets all of the latest E1 and T1 specifications, inclu ding the following: § ANSI: T1.403 - 1995, T1.231 - 1993, T1.408 § AT&T: TR54016, TR62411 § ITU: G.703, G.704, G.706, G.736, ...

  • Maxim DS21Q55 - page 4

    Product Preview DS21Q55 4 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 1.1 FEATURE HIGHLIGHTS The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 transceivers plus many new features. 1.1.1 General § 27mm, 1.27 pitch BGA ...

  • Maxim DS21Q55 - page 5

    Product Preview DS21Q55 5 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . § Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation § Can be placed in either the receive or transmit path or disabled § Limit trip ind ...

  • Maxim DS21Q55 - page 6

    Product Preview DS21Q55 6 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . § Hardware - signaling capability − Receive - signaling reinsertion to a backplane, multiframe sync − Availability of signaling in a separate PCM data stream − Signaling freezing § Ability to pass ...

  • Maxim DS21Q55 - page 7

    Product Preview DS21Q55 7 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Note: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125 µ s T1 frame, there are 24 8 - bit channels plus a framing bit. It is assumed that the framing ...

  • Maxim DS21Q55 - page 8

    Product Preview DS21Q55 8 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TABLE OF CONTENTS 1.1 FEATURE HIGHLIGHTS ............................................................................................................................ 4 1.1.1 General ...................... ...

  • Maxim DS21Q55 - page 9

    Product Preview DS21Q55 9 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 12. LOOPBACK CONFIGURATI ON ............................................................................................................. 68 12.1 P ER - C HANNEL L OOPBACK ................................ ...

  • Maxim DS21Q55 - page 10

    Product Preview DS21Q55 10 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3.4 Receive Packet Bytes Available ............................................................................................... 144 22.3.5 HDLC FIFOS ............................................... ...

  • Maxim DS21Q55 - page 11

    Product Preview DS21Q55 11 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 32.2 E1 M ODE ...................................................................................................................................................... 218 33. OPERATING PARAMETERS ......... ...

  • Maxim DS21Q55 - page 12

    Product Preview DS21Q55 12 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 1.2 DOCUMENT REVISION HISTORY 1) Initial Preliminary Release ...

  • Maxim DS21Q55 - page 13

    Product Preview DS21Q55 13 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 2. BLOCK DIAGRAM A simplified block diagram showing the major components of the DS21Q55 is shown in Figure 4 - 1. Details are shown in subsequent figures. The block diagram is then divided into three fun ...

  • Maxim DS21Q55 - page 14

    Product Preview DS21Q55 14 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 3. PIN FUNCTION DESCRIPTION 3.1 Transmit Side Pins Signal Name: TCLK x Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz or a 2.048MHz primary clock. Used to clock data throu gh the trans ...

  • Maxim DS21Q55 - page 15

    Product Preview DS21Q55 15 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Signal Name: TSYNC x Sign al Description: Transmit Sync Signal Type: Input/Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to outp ...

  • Maxim DS21Q55 - page 16

    Product Preview DS21Q55 16 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Signal Name: TNEGI x Signal Description: Transmit Negative Data I nput Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected ...

  • Maxim DS21Q55 - page 17

    Product Preview DS21Q55 17 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Signal Name: RSYNC x Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (IOCR1 .5 = 0) or multiframe (IOCR1. ...

  • Maxim DS21Q55 - page 18

    Product Preview DS21Q55 18 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Signal Name: BPCLK x Signal Description: Back Plane Clock Signal Type: Outpu t A user - selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin. Signal Name: RP ...

  • Maxim DS21Q55 - page 19

    Product Preview DS21Q55 19 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation. Signal Name: D0/AD0 to D7/AD7 Signal De ...

  • Maxim DS21Q55 - page 20

    Product Preview DS21Q55 20 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Si gnal Name: A7/ALE (AS ) Signal Description: A7 or Address Latch Enable(Address Strobe) Signal Type: Input In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed ...

  • Maxim DS21Q55 - page 21

    Product Preview DS21Q55 21 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Signal Name: JTCLK Signa l Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. Signal Name: J ...

  • Maxim DS21Q55 - page 22

    Product Preview DS21Q55 22 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Signal Name: TTIP x and TRING x Si gnal Description: Transmit Tip and Ring Signal Type: Output Analog line driver outputs. These pins connect via a 1:2 step - up transformer to the network. See Line Inte ...

  • Maxim DS21Q55 - page 23

    Product Preview DS21Q55 23 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 3.8 Pinout DS21Q55 PIN DESCRIPTION Table 5 - 1 NOTE: Signal is common to all transceivers unless otherwise stated PIN SYMBOL TYPE DESCRIPTION U3 A0 I Address Bus Bit 0 (lsb). L17 A1 I Address Bus Bit 1. ...

  • Maxim DS21Q55 - page 24

    Product Preview DS21Q55 24 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . PIN SYMBOL TYPE DESCRIPTION A20 DVSS2 – Digital Signal Ground. B11 DVSS2 – Digital Signal Ground. A5 DVSS3 – Digital Signal Ground. B7 DVSS3 – Digital Signal Ground. B9 DVSS3 – Digital Signal G ...

  • Maxim DS21Q55 - page 25

    Product Preview DS21Q55 25 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . PIN SYMBOL TYPE DESCRIPTION #1. D17 RFSYNC2 O Receive Fr ame Sync (before the receive elastic store), Transceiver #2. A2 RFSYNC3 O Receive Frame Sync (before the receive elastic store), Transceiver #3. V ...

  • Maxim DS21Q55 - page 26

    Product Preview DS21Q55 26 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . PIN SYMBOL TYPE DESCRIPTION D2 RSIGF3 O Receive Signaling Freeze Output, Transceiver #3. V16 RSIG F4 O Receive Signaling Freeze Output, Transceiver #4. G1 RSYNC1 I/O Receive Sync, Transceiver #1. D12 RSY ...

  • Maxim DS21Q55 - page 27

    Product Preview DS21Q55 27 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . PIN SYMBOL TYPE DESCRIPTION C6 TLINK3 I Transmit Link Data, Transceiver #3. T19 TLINK4 I Transmit Link Data, Transceiver #4. R1 TNEGI1 I Transmit Negative Data Input for the LIU, Transceiver #1. F19 TNEG ...

  • Maxim DS21Q55 - page 28

    Product Preview DS21Q55 28 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . PIN SYMBOL TYPE DESCRIPTION G18 TV SS2 – Transmit Analog Signal Ground. C5 TVSS3 – Transmit Analog Signal Ground. U18 TVSS4 – Transmit Analog Signal Ground. K3 WR* (R/W*) I Write Input (Read/Write) ...

  • Maxim DS21Q55 - page 29

    Product Preview DS21Q55 29 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 3.9 Package DS21Q55 Pin DIAGRAM, 27mm BGA Figure 5 - 1 The diagram shown below is the l ead pattern that will be placed on the target PCB. This is the same pattern that would be seen as viewed from the t ...

  • Maxim DS21Q55 - page 30

    Product Preview DS21Q55 30 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 4. PARALLEL PORT The DS21Q55 is controlled via a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus b y an external microcontroller or microprocessor. The DS21Q55 can operate with either Intel or Mo ...

  • Maxim DS21Q55 - page 31

    Product Preview DS21Q55 31 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION PAGE 26 Status Register 9 SR9 * 27 Interrupt Mask Register 9 IMR9 * 28 Per - Channel Point er Register PCPR * 29 Per - Channel Data Register 1 PCDR1 * 2A P ...

  • Maxim DS21Q55 - page 32

    Product Preview DS21Q55 32 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION PAGE 5A Transmit Signaling Register 11 TS11 * 5B Transmit Signaling Register 12 TS12 * 5C Transmit Signaling Register 13 TS13 * 5D Transmit Signaling Regis ...

  • Maxim DS21Q55 - page 33

    Product Preview DS21Q55 33 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION PAGE 8E Transmit Channel Blocking Register 3 TCBR3 * 8F Tran smit Channel Blocking Register 4 TCBR4 * 90 HDLC #1 Transmit Control H1TC * 91 HDLC #1 FIFO Co ...

  • Maxim DS21Q55 - page 34

    Product Preview DS21Q55 34 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION PAGE C2 Receive FDL Match Register 1 RFDLM1 * C3 Receive FDL Match Register 2 RFDLM2 * C4 Test Register TES T * C5 Interleave Bus Operation Control Registe ...

  • Maxim DS21Q55 - page 35

    Product Preview DS21Q55 35 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . ADDRESS R/W REGISTER NAME REGISTER ABBREVIATION PAGE F6 Test Register TEST * F7 Test Register TEST * F8 Test Register TEST * F9 Test Register TEST * FA Test Register TEST * FB Test Register TEST * FC Tes ...

  • Maxim DS21Q55 - page 36

    Product Preview DS21Q55 36 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 5. SPECIAL PER - CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per - channel basis use a special method for channel selection. The registers involved are t ...

  • Maxim DS21Q55 - page 37

    Product Preview DS21Q55 37 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: PCDR1 Register Description: Per - Channel Data Register 1 Register Address: 29 h Bit # 7 6 5 4 3 2 1 0 Name Default CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Register Name: PCDR2 Register Descriptio ...

  • Maxim DS21Q55 - page 38

    Product Preview DS21Q55 38 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 6. PROGRAMMING MODEL The DS21Q55 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset t ...

  • Maxim DS21Q55 - page 39

    Product Preview DS21Q55 39 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 6.1 Power - Up Sequence The DS21Q55 contains an on - chip power - up reset function, which automatically clears the writeable register space immediately after power is supplied to the device. The user ca ...

  • Maxim DS21Q55 - page 40

    Product Preview DS21Q55 40 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 6.2 Interrupt Handling Various alarms, conditions, and events in the DS21Q55 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All STATUS reg isters can be pr ...

  • Maxim DS21Q55 - page 41

    Product Preview DS21Q55 41 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . marked as “double interrupt bits.” An interrupt will be produced when the condition occurs and when it clears. 6.4 Information Registers Information registers operate the same as status registers exc ...

  • Maxim DS21Q55 - page 42

    Product Preview DS21Q55 42 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 7. CLOCK MAP Figure 9 - 1 shows the clock map of the DS21Q55. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is o ...

  • Maxim DS21Q55 - page 43

    Product Preview DS21Q55 43 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 8. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS21Q55 is configured via a set of nine control registers. Typically, the control registers are only accessed when the system is firs ...

  • Maxim DS21Q55 - page 44

    Product Preview DS21Q55 44 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: T1R CR2 Register Description: T1 Receive Control Register 2 Register Address: 04h Bit # 7 6 5 4 3 2 1 0 Name - RFM RB8ZS RSLC96 RZSE RZBTSI RJC RD4YM Default 0 0 0 0 0 0 0 0 Bit 0/Receive ...

  • Maxim DS21Q55 - page 45

    Product Preview DS21Q55 45 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address: 05h Bit # 7 6 5 4 3 2 1 0 Name TJC TFPT TCPT TSSE GB7S TFDLS TBL TYEL Default 0 0 0 0 0 0 0 0 Bit 0/Transmit Y ...

  • Maxim DS21Q55 - page 46

    Product Preview DS21Q55 46 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address: 06h Bit # 7 6 5 4 3 2 1 0 Name TB8ZS TSLC96 TZSE FBCT2 FBCT1 TD4YM TZBTSI TB7ZS Default 0 0 0 0 0 0 0 0 Bit 0/ ...

  • Maxim DS21Q55 - page 47

    Product Preview DS21Q55 47 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 07h Bit # 7 6 5 4 3 2 1 0 Name - - - - - TFM PDE TLOOP Default 0 0 0 0 0 0 0 0 Bit 0/Transmit Loop Code Enable ( ...

  • Maxim DS21Q55 - page 48

    Product Preview DS21Q55 48 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 8.2 T1 Transmit Transparency The softw are - signaling insertion - enable registers, SSIE1 – SSIE4, can be used to select signaling insertion from the transmit - signaling registers, TS1 – TS12, on a ...

  • Maxim DS21Q55 - page 49

    Product Preview DS21Q55 49 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: T1RDMR1 Register Descriptio n: T1 Receive Digital Milliwatt Enable Register 1 Register Address: 0Ch Bit # 7 6 5 4 3 2 1 0 Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Default 0 0 0 0 0 0 0 0 Bits ...

  • Maxim DS21Q55 - page 50

    Product Preview DS21Q55 50 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 8.4 T1 Information Register Register Name: INFO1 Register Description: Information Register 1 Register Address: 10h Bit # 7 6 5 4 3 2 1 0 Name RPDV TPDV COFA 8ZD 16ZD SEFE B8ZS FBE Default 0 0 0 0 0 0 0 ...

  • Maxim DS21Q55 - page 51

    Product Preview DS21Q55 51 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . T1 ALARM CRITERIA Table 10 - 1 ALARM SET CRITERIA CLEAR CRITERIA Blue Alarm (AIS) (Note 1) Over a 3ms window, five or fewer zeros are received Over a 3ms window, six or more zeros are received Yellow Ala ...

  • Maxim DS21Q55 - page 52

    Product Preview DS21Q55 52 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 9. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS21 Q55 is configured via a set of four control registers. Typically, the control registers are only accessed when the system is fir ...

  • Maxim DS21Q55 - page 53

    Product Preview DS21Q55 53 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . E1 SYNC/RESYNC CRITERIA Table 11 - 1 FRAME OR MULTIFRAME LEVEL SYNC CRITERIA RESYNC CRITERIA ITU SPEC. FAS FAS present in frame N and N + 2, and FAS not present in frame N + 1 Three consecutive incorrect ...

  • Maxim DS21Q55 - page 54

    Product Preview DS21Q55 54 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address: 35h Bit # 7 6 5 4 3 2 1 0 Name TFPT T16S TUA1 TSiS TSA1 THDB3 TG802 TCRC4 Default 0 0 0 0 0 0 0 0 Bit 0/Transm ...

  • Maxim DS21Q55 - page 55

    Product Preview DS21Q55 55 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address: 36h Bit # 7 6 5 4 3 2 1 0 Name Sa8S Sa7S Sa6S Sa5S Sa4S AE BE AAIS ARA Default 0 0 0 0 0 0 0 0 Bit 0/Automatic ...

  • Maxim DS21Q55 - page 56

    Product Preview DS21Q55 56 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 9.2 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automat ic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive side f ...

  • Maxim DS21Q55 - page 57

    Product Preview DS21Q55 57 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 9.3 E1 Information Registers Register Name: INFO3 Register Description: Information Register 3 Register Address: 12h Bit # 7 6 5 4 3 2 1 0 Name - - - - - CRCRC FASRC CASRC Default 0 0 0 0 0 0 0 0 Bit 0/C ...

  • Maxim DS21Q55 - page 58

    Product Preview DS21Q55 58 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . E1 ALARM CRITERIA Table 11 - 2 ALARM S ET CRITERIA CLEAR CRITERIA ITU SPEC. RLOS An RLOS condition exists on power - up prior to initial synchronization, when a re - sync criteria has been met, or when a ...

  • Maxim DS21Q55 - page 59

    Product Preview DS21Q55 59 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 10. COMMON CONTROL AND STA TUS REGISTERS Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 70h Bit # 7 6 5 4 3 2 1 0 Name - CRC4R SIE ODM DICAI TCSS1 TCSS0 RLOSF Defau ...

  • Maxim DS21Q55 - page 60

    Product Preview DS21Q55 60 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IDR Register Description: Device Identification Register Register Address: 0Fh Bit # 7 6 5 4 3 2 1 0 Name ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Default 1 0 1 1 X X X X Bits 0 to 3/Chip Revision ...

  • Maxim DS21Q55 - page 61

    Product Preview DS21Q55 61 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IMR2 Register Description: Interrupt Mask Re gister 2 Register Address: 19h Bit # 7 6 5 4 3 2 1 0 Name RYELC RUA1C FRCLC RLOSC RYEL RUA1 FRCL RLOS Default 0 0 0 0 0 0 0 0 Bit 0/Receive Los ...

  • Maxim DS21Q55 - page 62

    Product Preview DS21Q55 62 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0 Bit 0/Receive Remote Al arm Co ...

  • Maxim DS21Q55 - page 63

    Product Preview DS21Q55 63 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bit # 7 6 5 4 3 2 1 0 Name LSPARE LDN LUP LOTC LORC V52LNK RDMA RRA Default 0 0 0 0 0 0 0 0 Bit 0/Receiv e Remote ...

  • Maxim DS21Q55 - page 64

    Product Preview DS21Q55 64 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6 5 4 3 2 1 0 Name - RSA1 RSA0 TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0 Bit 0/Receive Align Frame Event (RAF). ...

  • Maxim DS21Q55 - page 65

    Product Preview DS21Q55 65 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bit # 7 6 5 4 3 2 1 0 Name - RSA1 RSA0 TMF TAF RMF RCMF RAF Default 0 0 0 0 0 0 0 0 Bit 0/Receive Align Frame Eve ...

  • Maxim DS21Q55 - page 66

    Product Preview DS21Q55 66 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 11. I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configuration Register 1 Registe r Address: 01h Bit # 7 6 5 4 3 2 1 0 Name RSMS RSMS2 RSMS1 RSIO TSDW TSM TSIO ODF Default ...

  • Maxim DS21Q55 - page 67

    Product Preview DS21Q55 67 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h Bit # 7 6 5 4 3 2 1 0 Name RCLKINV TCLKINV RSYNCINV TSYNCINV TSSYNCINV H100EN TSCLKM RSCLKM Defa ult 0 0 0 0 ...

  • Maxim DS21Q55 - page 68

    Product Preview DS21Q55 68 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 12. LOOPBACK CONFIGURATION Register Name: LBCR Register Description: Loopback Co ntrol Register Register Address: 4Ah Bit # 7 6 5 4 3 2 1 0 Name - - - LIUC LLB RLB PLB FLB Default 0 0 0 0 0 0 0 0 Bit 0/F ...

  • Maxim DS21Q55 - page 69

    Product Preview DS21Q55 69 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Bit 3/Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the device. Data being received at RTIP and RRING will be replaced with the data ...

  • Maxim DS21Q55 - page 70

    Product Preview DS21Q55 70 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 12.1 Per - Channel Loopback The per - channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off ...

  • Maxim DS21Q55 - page 71

    Product Preview DS21Q55 71 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: PCLR3 Register Description: Per - Channel Loopback Enable Register 3 Register Address: 4Dh Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0 Bits 0 ...

  • Maxim DS21Q55 - page 72

    Product Preview DS21Q55 72 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 13. ERROR COUNT REGISTERS The DS21Q55 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, ...

  • Maxim DS21Q55 - page 73

    Product Preview DS21Q55 73 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 13.1 Line Code Violation Count Register (LCVCR) T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive zeros. If the B8ZS mode is set for the receive side, then B8ZS code w ...

  • Maxim DS21Q55 - page 74

    Product Preview DS21Q55 74 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: LCVCR1 Register Description: Line Code Violation Count Register 1 Register Address: 42h Bit # 7 6 5 4 3 2 1 0 Name LCVC15 LCVC14 LCVC13 LCVC12 LCVC11 LCVC10 LCVC9 LCCV8 Default 0 0 0 0 0 0 ...

  • Maxim DS21Q55 - page 75

    Product Preview DS21Q55 75 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 13.2 Path Code Violation Count Register (PCVCR) T1 O peration The path - code violation - count register records either Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to op ...

  • Maxim DS21Q55 - page 76

    Product Preview DS21Q55 76 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: PCVCR1 Register Description: Path Code Violation Count Register 1 Register Address: 44h Bit # 7 6 5 4 3 2 1 0 Name PCVC15 PCVC14 PCVC13 PCVC12 PCVC11 PCVC10 PCVC9 PCVC8 Default 0 0 0 0 0 0 ...

  • Maxim DS21Q55 - page 77

    Product Preview DS21Q55 77 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . The FOSCR1 (FOSCR1 ) is the most significant word and FOSCR2 is the least significant word of a 16 - bit counter that records frames out of sync. ...

  • Maxim DS21Q55 - page 78

    Product Preview DS21Q55 78 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: FOSCR1 Register Description: Frames Out Of Sync Count Register 1 Register Address: 46h Bit # 7 6 5 4 3 2 1 0 Name FOS15 FOS14 FOS13 FOS12 FOS11 FOS10 FOS9 FOS8 Default 0 0 0 0 0 0 0 0 Bits ...

  • Maxim DS21Q55 - page 79

    Product Preview DS21Q55 79 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 14. DS0 MONITORING FUNCTION The DS21Q55 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit directio ...

  • Maxim DS21Q55 - page 80

    Product Preview DS21Q55 80 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 14.2 Receive DS0 Monitor Registers Register Name: RDS0SEL Register Description: Receive Channel Monitor Select Register Address: 76h Bit # 7 6 5 4 3 2 1 0 Name - - - RCM4 RCM3 RCM2 RCM1 RCM0 Default 0 0 ...

  • Maxim DS21Q55 - page 81

    Product Preview DS21Q55 81 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15. SIGNALING OPERATION There are t wo methods to access receive signaling data and provide transmit signaling data: processor - based (i.e., software - based) or hardware - based. Processor - based refe ...

  • Maxim DS21Q55 - page 82

    Product Preview DS21Q55 82 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.1.1 Processor - Based Receive Signaling The robbe d - bit signaling (T1) or TS16 CAS signaling (E1) is sampled in the receive data stream and copied into the receive signaling registers, RS1 through R ...

  • Maxim DS21Q55 - page 83

    Product Preview DS21Q55 83 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . register s for T1 mode and PCDR1 - PCDR4 registers for E1 mode. In E1 mode, the user will generally select all channels when doing reinsertion. 15.1.2.2 Force Receive Signaling All Ones In T1 mode, the u ...

  • Maxim DS21Q55 - page 84

    Product Preview DS21Q55 84 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RS1 to RS12 Register Description: Receive Signaling Registers (T1 Mode, ESF Format) Register Address: 60h to 6Bh (MSB) (LSB) CH2 - A CH2 - B CH2 - C CH2 - D CH1 - A CH1 - B CH1 - C CH1 - D ...

  • Maxim DS21Q55 - page 85

    Product Preview DS21Q55 85 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RS1 to RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Format) Register Address: 60h to 6Fh (MSB) (LSB) 0 0 0 0 X Y X X RS1 CH 2 - A CH2 - B CH2 - C CH2 - D CH1 - A CH ...

  • Maxim DS21Q55 - page 86

    Product Preview DS21Q55 86 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RSCSE1 , RSCSE2 , RSCSE3 , RSCSE4 Register Description: Receive Signaling Change Of State Interrupt Enable Register Addre ss: 3Ch, 3Dh, 3Eh, 3Fh (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 ...

  • Maxim DS21Q55 - page 87

    Product Preview DS21Q55 87 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.2 Transmit Signaling SIMPLIFIED DIAGRAM OF TRANSMIT SIGNALING PATH Figure 17 - 2 15.2.1 Processor - Based Transmit Signaling In processor - based mode, signaling data is loaded into the t ransmit - si ...

  • Maxim DS21Q55 - page 88

    Product Preview DS21Q55 88 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.2.1.1 T1 Mode In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1 – TS12 contain a full multiframe of signaling data. In T1 D4 framing mode, there are only two si ...

  • Maxim DS21Q55 - page 89

    Product Preview DS21Q55 89 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS Format) Register Address: 50h to 5Fh (MSB) (LSB) 0 0 0 0 X Y X X T S1 CH2 - A CH2 - B CH2 - C CH2 - D CH1 - A C ...

  • Maxim DS21Q55 - page 90

    Product Preview DS21Q55 90 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CCS Format) Register Address: 50h to 5F h (MSB) (LSB) 1 2 3 4 5 6 7 8 TS1 17 18 19 20 9 10 11 12 TS2 33 34 35 36 25 ...

  • Maxim DS21Q55 - page 91

    Product Preview DS21Q55 91 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (T1 Mode, ESF Format) Register Address: 50h to 5Bh (MSB) (LSB) CH2 - A CH2 - B CH2 - C CH2 - D CH1 - A CH1 - B CH1 - C CH1 - ...

  • Maxim DS21Q55 - page 92

    Product Preview DS21Q55 92 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . R egister Name: TS1 to TS16 Register Description: Transmit Signaling Registers (T1 Mode, D4 Format) Register Address: 50h to 5Bh (MSB) (LSB) CH2 - A CH2 - B CH2 - A CH2 - B CH1 - A CH1 - B CH1 - A CH1 - ...

  • Maxim DS21Q55 - page 93

    Product Preview DS21Q55 93 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS si gnaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling dat ...

  • Maxim DS21Q55 - page 94

    Product Preview DS21Q55 94 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Address: 0Ah Bit # 7 6 5 4 3 2 1 0 Name CH22 CH21 CH20 CH19 CH18 CH17 CH16 LCAW Default 0 0 0 0 0 0 0 0 Bit 0/Low ...

  • Maxim DS21Q55 - page 95

    Product Preview DS21Q55 95 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 15.2.3 Software Signaling Insertion Enable Registers, T1 Mode In T1 mode, only registers SSIE1 through SSIE3 are used since t here are only 24 channels in a T1 frame. Register Name: SSIE1 Register Descri ...

  • Maxim DS21Q55 - page 96

    Product Preview DS21Q55 96 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 17.2.4 Hardware - Based Transmit Signaling In hardware - based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSE ...

  • Maxim DS21Q55 - page 97

    Product Preview DS21Q55 97 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 16. PER - CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per - channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channe ...

  • Maxim DS21Q55 - page 98

    Product Preview DS21Q55 98 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 16.1 Idle Code Programming Examples The following e xample sets transmit channel 3 idle code to 7Eh: Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set idle code to 7Eh The following ...

  • Maxim DS21Q55 - page 99

    Product Preview DS21Q55 99 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IAAR Register Description: Idle Array Address Register Register Address: 7Eh Bit # 7 6 5 4 3 2 1 0 Name GRIC GTIC IAA5 IAA4 IAA3 IAA2 IAA1 IAA0 Default 0 0 0 0 0 0 0 0 Bits 0 to 5/Channel ...

  • Maxim DS21Q55 - page 100

    Product Preview DS21Q55 100 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 1 = insert data from the idle code array into the transmit data stream ...

  • Maxim DS21Q55 - page 101

    Product Preview DS21Q55 101 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TCICE3 Register Description: Transmit Channel Idle Code Enable Register 3 Register Address: 82h Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0 ...

  • Maxim DS21Q55 - page 102

    Product Preview DS21Q55 102 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RCICE3 Register Description: Receive Ch annel Idle Code Enable Register 3 Register Address: 86h Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0 ...

  • Maxim DS21Q55 - page 103

    Product Preview DS21Q55 103 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 17. CHANNEL BLOCKING REGISTERS The receive - channel blocking registers (RCBR1 /RCBR2 /RCBR3 /RCBR4 ) and the transmit - channel blocking r egisters (TCBR1 /TCBR2 /TCBR3 /TCBR4 ) control the RCHBLK and ...

  • Maxim DS21Q55 - page 104

    Product Preview DS21Q55 104 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RCBR3 Register Description: Receive Channel Blocking Register 3 Register Address: 8Ah Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0 Bits 0 to ...

  • Maxim DS21Q55 - page 105

    Product Preview DS21Q55 105 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TCBR3 Register Description: Transmit Channel Blocking Register 3 Register Address: 8Eh Bit # 7 6 5 4 3 2 1 0 Name CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 Default 0 0 0 0 0 0 0 0 Bits 0 to ...

  • Maxim DS21Q55 - page 106

    Product Preview DS21Q55 106 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 18. ELASTIC STORES OPERATION The DS21Q55 contains dual t wo - frame, fully independent elastic stores, one for the receive direction and one for the transmit direction. The transmit - and receive - side ...

  • Maxim DS21Q55 - page 107

    Product Preview DS21Q55 107 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: ESCR Register Descripti on: Elastic Store Control Register Register Address: 4Fh Bit # 7 6 5 4 3 2 1 0 Name TESALGN TESR TESMDM TESE RESALGN RESR RESMDM RESE Default 0 0 0 0 0 0 0 0 Bit 0 ...

  • Maxim DS21Q55 - page 108

    Product Preview DS21Q55 108 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6 5 4 3 2 1 0 Name - - TESF TESEM TSLIP RESF RESEM RSLIP Default 0 0 0 0 0 0 0 0 Bit 0/Receive Elastic Store Slip ...

  • Maxim DS21Q55 - page 109

    Product Preview DS21Q55 109 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . ...

  • Maxim DS21Q55 - page 110

    Product Preview DS21Q55 110 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 18.1 Receive Side See the IOCR1 and IOCR2 registers for information on clock and I/O configurations. If the receive - side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048 ...

  • Maxim DS21Q55 - page 111

    Product Preview DS21Q55 111 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 18.2 Transmit Side See the IOCR1 and IOCR2 registers for information on clock and I/O configurations. The operation of the transmit elastic store is very similar to the receive side. If the transmit - s ...

  • Maxim DS21Q55 - page 112

    Product Preview DS21Q55 112 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . respective network clock signals, the elastic store reset bits (ESCR.2 and ESCR.6) should be toggled from a zero to a one to ensure proper operation. ...

  • Maxim DS21Q55 - page 113

    Product Preview DS21Q55 113 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 19. G.706 INT ERMEDIATE CRC - 4 UPDATING (E1 MODE ONLY) The DS21Q55 can implement the G.706 CRC - 4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSE ...

  • Maxim DS21Q55 - page 114

    Product Preview DS21Q55 114 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 20. T1 BIT ORIENTED CODE (BOC) CONTROLLER The DS21Q55 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function i s available only in T1 mode. 20.1 Transmit ...

  • Maxim DS21Q55 - page 115

    Product Preview DS21Q55 115 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: BOCC Register Description: BOC Control R egister Register Address: 37h Bit # 7 6 5 4 3 2 1 0 Name - - - RBOCE RBR RBF1 RBF0 SBOC Default 0 0 0 0 0 0 0 0 Bit 0/Send BOC (SBOC). Set = 1 to ...

  • Maxim DS21Q55 - page 116

    Product Preview DS21Q55 116 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RFDL (RFDL register bit usage when BOCC .4 = 1) Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 5 4 3 2 1 0 N ame - - RBOC5 RBOC4 RBOC3 RBOC2 RBOC1 RBOC0 Defaul ...

  • Maxim DS21Q55 - page 117

    Product Preview DS21Q55 117 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IMR8 Register Description: Interrupt Mask Register 8 Register Address: 25h Bit # 7 6 5 4 3 2 1 0 Name - - BOCC RFDLAD RFDLF TFDLE RMTCH RBOC Default 0 0 0 0 0 0 0 0 Bit 0/Receive BOC Dete ...

  • Maxim DS21Q55 - page 118

    Product Preview DS21Q55 118 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 21. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) The DS21Q55, when operated in the E1 mode, provides for access to both the Sa and the Si bits via three different methods. The first me ...

  • Maxim DS21Q55 - page 119

    Product Preview DS21Q55 119 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RAF Register Description: Receive Align Frame Register Register Address: C6h Bit # 7 6 5 4 3 2 1 0 Name Si 0 0 1 1 0 1 1 Default 0 0 0 0 0 0 0 0 Bit 0/Frame Al ignment Signal Bit (1). Bit ...

  • Maxim DS21Q55 - page 120

    Product Preview DS21Q55 120 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TAF Register Description: Transmit Align Frame Register Register Address: D0h Bit # 7 6 5 4 3 2 1 0 Name Si 0 0 1 1 0 1 1 Default 0 0 0 1 1 0 1 1 Bit 0/Frame Alignment Signal Bit (1). Bit ...

  • Maxim DS21Q55 - page 121

    Product Preview DS21Q55 121 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 21.3 Internal Register Scheme Based On CRC4 Multiframe (Method 3) On the receive side, the re is a set of eight registers (RSiAF , RSiNAF , RRA , RSa4 to RSa8 ) that report the Si and Sa bits as they ar ...

  • Maxim DS21Q55 - page 122

    Product Preview DS21Q55 122 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RSiNAF Register Description: Receive Si Bits of the Nonalign Frame Register Address: C9h Bit # 7 6 5 4 3 2 1 0 Name SiF1 SiF3 SiF5 SiF7 SiF9 SiF11 SiF13 SiF15 Default 0 0 0 0 0 0 0 0 Bit ...

  • Maxim DS21Q55 - page 123

    Product Preview DS21Q55 123 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RSa4 Register Description: Receive Sa4 Bits Register Address: CBh Bit # 7 6 5 4 3 2 1 0 Name RSa4F1 RSa4F3 RSa4F5 RSa4F7 RSa4F9 RSa4F11 RSa4F13 RSa4F15 Default 0 0 0 0 0 0 0 0 Bit 0/Sa4 B ...

  • Maxim DS21Q55 - page 124

    Product Preview DS21Q55 124 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RSa6 Register Description: Receive Sa6 Bits Register Address: CDh Bit # 7 6 5 4 3 2 1 0 Na me RSa6F1 RSa6F3 RSa6F5 RSa6F7 RSa6F9 RSa6F11 RSa6F13 RSa6F15 Default 0 0 0 0 0 0 0 0 Bit 0/Sa6 ...

  • Maxim DS21Q55 - page 125

    Product Preview DS21Q55 125 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RSa8 Register Description: Receive Sa8 Bits Register Address: CFh Bit # 7 6 5 4 3 2 1 0 Name RSa8F1 RSa8F3 RSa8F5 RSa8F7 RSa8F9 RSa8F11 RSa8F13 RSa8F15 Default 0 0 0 0 0 0 0 0 Bit 0/Sa8 B ...

  • Maxim DS21Q55 - page 126

    Product Preview DS21Q55 126 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TSiAF Register Description: Transmit Si Bits of the Align Frame Register Address: D2h Bit # 7 6 5 4 3 2 1 0 Name TsiF0 TsiF2 T siF4 TsiF6 TsiF8 TsiF10 TsiF12 TsiF14 Default 0 0 0 0 0 0 0 ...

  • Maxim DS21Q55 - page 127

    Product Preview DS21Q55 127 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TSiNAF Register Description: Transmit Si Bits of the Nonalign Frame Register Address: D3h Bit # 7 6 5 4 3 2 1 0 Name TsiF1 TsiF3 TsiF5 TsiF7 TsiF9 TsiF11 TsiF13 TSiF15 Default 0 0 0 0 0 0 ...

  • Maxim DS21Q55 - page 128

    Product Preview DS21Q55 128 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TSa4 Register Description: Transmit Sa4 Bits Register Address: D5h Bit # 7 6 5 4 3 2 1 0 Name TSa4F1 TSa4F 3 TSa4F5 TSa4F7 TSa4F9 TSa4F11 TSa4F13 TSa4F15 Default 0 0 0 0 0 0 0 0 Bit 0/Sa4 ...

  • Maxim DS21Q55 - page 129

    Product Preview DS21Q55 129 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TSa6 Register Description: Transmit Sa6 Bits Register Address: D7h Bit # 7 6 5 4 3 2 1 0 Name TSa6F1 TSa6F3 TSa6F5 TSa6F7 TSa6F9 TSa6F11 TSa6F13 TSa6F15 Default 0 0 0 0 0 0 0 0 Bit 0/Sa6 ...

  • Maxim DS21Q55 - page 130

    Product Preview DS21Q55 130 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TSa8 Register Description: Transmit Sa8 Bits Register Address: D9h Bit # 7 6 5 4 3 2 1 0 Name TSa8F1 TSa8F3 TSa8F5 TSa8F7 TSa8F9 TSa8F11 TSa8F13 TSa8F1 5 Default 0 0 0 0 0 0 0 0 Bit 0/Sa8 ...

  • Maxim DS21Q55 - page 131

    Product Preview DS21Q55 131 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address: DAh Bit # 7 6 5 4 3 2 1 0 Name SiAF SiNAF RA Sa4 Sa5 Sa6 Sa7 Sa8 Default 0 0 0 0 0 0 0 0 Bit 0/Additional Bi ...

  • Maxim DS21Q55 - page 132

    Product Preview DS21Q55 132 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22. HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode). Each ...

  • Maxim DS21Q55 - page 133

    Product Preview DS21Q55 1 33 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . HDLC CONTROLLER REGISTERS Table 24 - 1 NAME FUNCTION CONTROL/CONFIGURATION H1TC , HDLC #1 Transmit Control Register H2TC , HDLC #2 Transmit Control Register General control over the transmit HDLC contr ...

  • Maxim DS21Q55 - page 134

    Product Preview DS21Q55 134 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.2 HDLC Configuration Basic configuration of the HDLC controllers is accomplished via the HxTC and HxRC registers. Operating features such as CRC generation, zero stuffer, transmit and receive HDLC ma ...

  • Maxim DS21Q55 - page 135

    Product Preview DS21Q55 135 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: H1RC , H2RC Register Description: HDLC #1 Receive Control, HDLC #2 Receive Control Register Address: 31h, 32h Bit # 7 6 5 4 3 2 1 0 Name RHR RHMS - - - - - RSFD Default 0 0 0 0 0 0 0 0 Bi ...

  • Maxim DS21Q55 - page 136

    Product Preview DS21Q55 136 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.2.1 FIFO Control Control of the transmit and receive FIFOs is accomplished via the FIFO control (HxFC). The FIFO control register sets the watermarks for both the transmit and receive FIFO. Bits 3 ? ...

  • Maxim DS21Q55 - page 137

    Product Preview DS21Q55 137 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3 HDLC Mapping 22.3.1 Receive The HDLC controllers need to be assigned a space in the T1/E1 bandwidth in which they will transmit a nd receive data. The controllers can be mapped to either the FDL (T ...

  • Maxim DS21Q55 - page 138

    Product Preview DS21Q55 138 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: H1RTSBS , H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select Register Address: 96h, A6h Bit # 7 6 5 4 3 2 1 0 Name ...

  • Maxim DS21Q55 - page 139

    Product Preview DS21Q55 139 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3.2 Transmit The HxTCS1 – HxTCS4 registers are used to assign the transmit controllers to channels 1 – 24 (T1) or 1– 32 (E1), according to the following table. REG ISTER CHANNELS HxTCS1 1–8 H ...

  • Maxim DS21Q55 - page 140

    Product Preview DS21Q55 140 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: H1TTSBS , H2TTSBS Register Description: H DLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select Register Address: 9Bh, Abh Bit # 7 6 5 4 3 2 1 0 N ...

  • Maxim DS21Q55 - page 141

    Product Preview DS21Q55 141 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: SR6 , SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Regi ster 7 Register Address: 20h, 22h Bit # 7 6 5 4 3 2 1 0 Name - TMEND RPE RPS RHWM RNE TLWM TNF Default 0 0 0 ...

  • Maxim DS21Q55 - page 142

    Product Preview DS21Q55 142 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IMR6 , IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 Register Address: 21h, 23h Bit # 7 6 5 4 3 2 1 0 Name - TMEND RPE RPS RHWM RNE TLWM ...

  • Maxim DS21Q55 - page 143

    Product Preview DS21Q55 143 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: INFO5 , INFO6 Register Description: HDLC #1 Information Register HDLC #2 Information Register Register Address: 2Eh, 2Fh Bit # 7 6 5 4 3 2 1 0 Name - - TEMPTY TFULL REMPTY PS2 PS1 PS0 Def ...

  • Maxim DS21Q55 - page 144

    Product Preview DS21Q55 144 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3.3 FIFO Information The transmit FIFO buffer - available register indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how ma ...

  • Maxim DS21Q55 - page 145

    Product Preview DS21Q55 145 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.3.5 HDLC FIFOS Register Name: H1TF , H2TF Register Description: HDLC # 1 Transmit FIFO, HDLC # 2 Transmit FIFO Register Address: 9Dh, Adh Bit # 7 6 5 4 3 2 1 0 Name THD7 THD6 THD5 THD4 THD3 THD2 THD1 ...

  • Maxim DS21Q55 - page 146

    Product Preview DS21Q55 146 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.4 Receive HDLC Code Example Below is an example of a receive HDLC routine for controller #1. 1) Reset receive HDLC controller 2) Set HDLC mode, mapping, and high watermark 3) Start new message buffer ...

  • Maxim DS21Q55 - page 147

    Product Preview DS21Q55 147 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RFDL Register Description: Receive FDL Register Register Address: C0h Bit # 7 6 5 4 3 2 1 0 Name RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0 Default 0 0 0 0 0 0 0 0 Bit 0/Receive FDL ...

  • Maxim DS21Q55 - page 148

    Product Preview DS21Q55 148 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 22.5.2 Transmit Section The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL regist ...

  • Maxim DS21Q55 - page 149

    Product Preview DS21Q55 149 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23. LINE INTERFACE UNIT (LIU) The LIU in the DS21Q55 contains three sections: the receiver, which handles clock and data recovery; the transmitter, whic h wave - shapes and drives the network line; and ...

  • Maxim DS21Q55 - page 150

    Product Preview DS21Q55 150 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.1 LIU Operation The analog AMI/HDB 3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is transformer coupled into the RTIP and RRING pins of the DS21Q55. The user has the optio ...

  • Maxim DS21Q55 - page 151

    Product Preview DS21Q55 151 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.2.1 Receive Level Indicator and Threshold Interrupt The DS21 Q 55 reports the signal strength at RTIP and RRING in 2.5dB increments through RL3 – RL0 located in Information Register 2 (INFO2 ). Thi ...

  • Maxim DS21Q55 - page 152

    Product Preview DS21Q55 152 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.3 LIU Transm itter The DS21Q55 uses a phase - lock loop along with a precision digital - to - analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms ...

  • Maxim DS21Q55 - page 153

    Product Preview DS21Q55 153 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.4 MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI spe ...

  • Maxim DS21Q55 - page 154

    Product Preview DS21Q55 154 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.7 LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control 1 Register Address: 78h Bit # 7 6 5 4 3 2 1 0 Name L2 L1 L0 EGL JAS JABDS DJA TPD Default 0 0 0 0 0 0 0 0 Bit ...

  • Maxim DS21Q55 - page 155

    Product Preview DS21Q55 155 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . E1 Mode L2 L1 L0 A PPLICATION N (1) RETURN LOSS Rt (1) 0 0 0 75O normal 1:2 NM 0 0 0 1 120O normal 1:2 NM 0 1 0 0 75O with high return loss* 1:2 21dB 6.2O 1 0 1 120O with high return loss* 1:2 21dB 11.6 ...

  • Maxim DS21Q55 - page 156

    Product Preview DS21Q55 156 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TLBC Register Description: Transmit Line Build - Out Control Register Address: 7Dh Bit # 7 6 5 4 3 2 1 0 Name - A GCE GC5 GC4 GC3 GC2 GC1 GC0 Default 0 0 0 0 0 0 0 0 Bit 0 – 5 Gain Cont ...

  • Maxim DS21Q55 - page 157

    Product Preview DS21Q55 157 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 79h Bit # 7 6 5 4 3 2 1 0 Name ETS LIRST IBPV TUA1 JAMUX - SCLD CLDS Default 0 0 0 0 0 0 0 0 Bit 0 Custom Line Driver ...

  • Maxim DS21Q55 - page 158

    Product Preview DS21Q55 158 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bit # 7 6 5 4 3 2 1 0 Name - TCES RCES MM1 MM0 RSCLKE TSCLKE TAOZ Default 0 0 0 0 0 0 0 0 Bit 0/Transmit Alternat ...

  • Maxim DS21Q55 - page 159

    Product Preview DS21Q55 159 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 7Bh Bit # 7 6 5 4 3 2 1 0 Name CMIE CMII MPS1 MPS 0 TT1 TT0 RT1 RT0 Default 0 0 0 0 0 0 0 0 Bits 0 to 1/Receive Termi ...

  • Maxim DS21Q55 - page 160

    Product Preview DS21Q55 160 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: INFO2 Register Description: Information Register 2 Register Address: 11h Bit # 7 6 5 4 3 2 1 0 Name BSYNC - TCLE TOCD RL3 RL2 RL1 RL0 Default 0 0 0 0 0 0 0 0 Bits 0 to 3/Receive Level Bit ...

  • Maxim DS21Q55 - page 161

    Product Preview DS21Q55 161 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: CCR4 Register Description: Common Control Register 4 Register Address: 73h Bit # 7 6 5 4 3 2 1 0 Name RLT3 RLT2 RLT1 RLT0 — — — — Default 0 0 0 0 0 0 0 0 Bit 0 /Unused, must be se ...

  • Maxim DS21Q55 - page 162

    Product Preview DS21Q55 162 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Regi ster Name: SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6 5 4 3 2 1 0 Name ILUT TIMER RSCOS JALT LRCL TCLE TOCD LOLITC Default 0 0 0 0 0 0 0 0 Bit 0/Loss of Line Interf ...

  • Maxim DS21Q55 - page 163

    Product Preview DS21Q55 163 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IMR1 Registe r Description: Interrupt Mask Register 1 Register Address: 17h Bit # 7 6 5 4 3 2 1 0 Name - TIMER RSCOS JALT LRCL TCLE TOCD LOLITC Default 0 0 0 0 0 0 0 0 Bit 0/Loss of Trans ...

  • Maxim DS21Q55 - page 164

    Product Preview DS21Q55 164 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.8 Recommended Circuits BASIC INTERFACE Figure 25 - 4 NOTES: 1) All resistor values are ±1%. 2) Resistors R should be set to 60O each if the internal receive - side termination feature is enabled. Wh ...

  • Maxim DS21Q55 - page 165

    Product Preview DS21Q55 165 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . PROTECTED INTERFAC E USING INTERNAL RECEIVE TERMINATION Figure 25 - 5 NOTES: 1) All resistor values are ±1%. 2) X1 and X2 are very low DCR transformers 3) C1 = 1µF ceramic. 4) S1 and S2 are 6V transie ...

  • Maxim DS21Q55 - page 166

    Product Preview DS21Q55 166 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 23.9 Component Specifications TRANSFORMER SPECIFICATIONS Table 25 - 1 SPECIFIC ATION RECOMMENDED VALUE Turns Ratio 3.3V Applications 1:1 (receive) and 1:2 (transmit) ±2% Primary Inductance 600 µ H min ...

  • Maxim DS21Q55 - page 167

    Product Preview DS21Q55 167 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . E1 TRANSMIT PULSE TEMPLATE Figure 25 - 6 T1 TRANSMIT PULSE TEMPLATE Figure 25 - 7 0 -0.1 -0.2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 TIME (ns) SCALED AMPLITUDE 50 100 150 200 250 -50 -100 -15 ...

  • Maxim DS21Q55 - page 168

    Product Preview DS21Q55 168 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . JITTER TOLERANCE (T1 MODE) Figure 25 - 8 JITTER TOLE RANCE (E1 MODE) Figure 25 - 9 FREQUENCY (Hz) UNIT INTERVALS (UIpp) 1K 100 10 1 0.1 10 100 1K 10K 100K DS21Q55 Tolerance 1 TR 62411 (Dec. 90) ITU-T G. ...

  • Maxim DS21Q55 - page 169

    Product Preview DS21Q55 169 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . JITTER ATTENUATION (T1 MODE) Figure 25 - 10 JITTER ATTENUATION (E1 MODE) Figure 25 - 11 FREQUENCY (Hz) 0dB -20dB -40dB -60dB 1 10 100 1K 10K JITTER ATTENUATION (dB) 100K TR 62411 (Dec. 90) Prohibited Ar ...

  • Maxim DS21Q55 - page 170

    Product Preview DS21Q55 170 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 24. PROGRAMMABLE IN - BAND LOOP CODE GENERATION AND DETECTION The DS21Q55 has the ability to generate and detect a repeating bit pattern from 1 bit to 8 bits or 16 bits in length. This function is avail ...

  • Maxim DS21Q55 - page 171

    Product Preview DS21Q55 171 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IBCC Register Description: In - Band Code Control Register Register Address: B6h Bit # 7 6 5 4 3 2 1 0 Name TC1 TC0 RUP2 RUP1 RUP0 RDN2 RDN1 RDN0 Default 0 0 0 0 0 0 0 0 Bits 0 to 2/Recei ...

  • Maxim DS21Q55 - page 172

    Product Preview DS21Q55 172 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: TCD1 Register Description: Transmit Code Definition Register 1 Register Address: B7h Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Bit 0/Transmit Code Definit ...

  • Maxim DS21Q55 - page 173

    Product Preview DS21Q55 173 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RUPCD1 Register Description: Receive - Up Code Definition Register 1 Register Address: B9h Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Note: Writing this re ...

  • Maxim DS21Q55 - page 174

    Product Preview DS21Q55 174 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Regist er Name: RDNCD1 Register Description: Receive - Down Code Definition Register 1 Register Address: BBh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Note: Writing this ...

  • Maxim DS21Q55 - page 175

    Product Preview DS21Q55 175 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RDNCD2 Register Description: Receive - Down Code Definition Register 2 Register Address: BCh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Bit 0/ Receive - Do ...

  • Maxim DS21Q55 - page 176

    Product Preview DS21Q55 176 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: RSCD1 Register Description: Receive - Spare Code Definition Register 1 Register Address: BEh Bit # 7 6 5 4 3 2 1 0 Name C7 C6 C5 C4 C3 C2 C1 C0 Default 0 0 0 0 0 0 0 0 Note: Writing this ...

  • Maxim DS21Q55 - page 177

    Product Preview DS21Q55 177 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25. BERT FUNCTION The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating - bit patterns. It is used to test and stress data - communication links. The BERT block ...

  • Maxim DS21Q55 - page 178

    Product Preview DS21Q55 178 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25.1 BERT Register Description Register Name: BC1 Register Description: BERT Control Register 1 Register Address: E0h Bit # 7 6 5 4 3 2 1 0 Name TC TINV RINV PS2 PS1 PS0 LC RESYNC Default 0 0 0 0 0 0 0 ...

  • Maxim DS21Q55 - page 179

    Product Preview DS21Q55 179 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: BC2 Register Description: BERT Control Regi ster 2 Register Address: E1h Bit # 7 6 5 4 3 2 1 0 Name EIB2 EIB1 EIB0 SBE RPL3 RPL2 RPL1 RPL0 Default 0 0 0 0 0 0 0 0 Bits 0 to 3/Repetitive P ...

  • Maxim DS21Q55 - page 180

    Product Preview DS21Q55 180 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: BIC Register Description: BER T Interface Control Register Register Address: EAh Bit # 7 6 5 4 3 2 1 0 Name - RFUS - TBAT TFUS - BERTDIR BERTEN Default 0 0 0 0 0 0 0 0 Bit 0/BERT Enable ( ...

  • Maxim DS21Q55 - page 181

    Product Preview DS21Q55 181 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: SR9 Register Description: Status Register 9 Register Address: 26h Bit # 7 6 5 4 3 2 1 0 Name - BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC Default 0 0 0 0 0 0 0 0 Bit 0/BERT in Synchronization C ...

  • Maxim DS21Q55 - page 182

    Product Preview DS21Q55 182 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IMR9 Register Description: Interrupt Mask Register 9 Register Addres s: 27h Bit # 7 6 5 4 3 2 1 0 Name - BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC Default 0 0 0 0 0 0 0 0 Bit 0/BERT in Synchro ...

  • Maxim DS21Q55 - page 183

    Product Preview DS21Q55 183 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25.2 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pat ...

  • Maxim DS21Q55 - page 184

    Product Preview DS21Q55 184 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25.3 BERT Bit Counter Once BERT has achieved synchronization, this 32 - bit counter will increment for each data bit (i.e., clock) received . Toggling the LC control bit in BC1 can clear this counter, w ...

  • Maxim DS21Q55 - page 185

    Product Preview DS21Q55 185 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 25.4 BERT Error Counter Once BERT has achieved synchronization, this 24 - bit counter will increment for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This ...

  • Maxim DS21Q55 - page 186

    Product Preview DS21Q55 186 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 26. PAYLOAD ERROR INSERTION FUNCTION An error - insertion function is available in the DS21Q55 and is used to create errors in t he payload portion of the T1 frame in the transmit path. Errors can be in ...

  • Maxim DS21Q55 - page 187

    Product Preview DS21Q55 187 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: ERC Register Description: Error Rate Control Register Regist er Address: EBh Bit # 7 6 5 4 3 2 1 0 Name WNOE - - CE ER3 ER2 ER1 ER0 Default 0 0 0 0 0 0 0 0 Bits 0 to 3/Error Insertion Rat ...

  • Maxim DS21Q55 - page 188

    Product Preview DS21Q55 188 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 26.1 Number Of Error Registers The number of error registers determine how many errors will be generated. Up to 1023 errors can be gen erated. The host will load the number of errors to be generated int ...

  • Maxim DS21Q55 - page 189

    Product Preview DS21Q55 189 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 26.1.1 Number Of Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted. Register Name: NOEL1 Register Description: Number Of Errors ...

  • Maxim DS21Q55 - page 190

    Product Preview DS21Q55 190 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 27. INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q55 can ...

  • Maxim DS21Q55 - page 191

    Product Preview DS21Q55 191 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: IBOC Register Description: Interleave Bus Operation Control Register Register Address: C5h Bit # 7 6 5 4 3 2 1 0 Name - IBS1 IBS0 IBOSEL IBOEN DA2 DA1 DA0 Default 0 0 0 0 0 0 0 0 Bits 0 t ...

  • Maxim DS21Q55 - page 192

    Product Preview DS21Q55 192 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . IBO EXAMPLE Figure 29 - 1 RSYSCLK TSYSCLK RSYNC TSSYNC RSIG TSIG TSER RSER RSYSCLK TSYSCL K RSIG TSIG TSER RSER RSYSCLK TSYSCLK RSIG TSIG TSER RSER RSYSCLK TSYSCLK RSIG TSIG TSER RSER 8.192MHz System Cl ...

  • Maxim DS21Q55 - page 193

    Product Preview DS21Q55 193 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 28. EXTENDED SYSTEM INFORMATION BUS (ESIB) The ESI B allows two DS21Q55s to share an 8 - bit CPU bus for the purpose of reporting alarms and interrupt status as a group. With a single bus read, the host ...

  • Maxim DS21Q55 - page 194

    Product Preview DS21Q55 194 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: ESIBCR1 Register Description: Extended System Information Bus Control Register 1 Register Address: B0h Bit # 7 6 5 4 3 2 1 0 Name - - - - ESIBSEL2 ESIBSE L1 ESIBSEL0 ESIEN Default 0 0 0 0 ...

  • Maxim DS21Q55 - page 195

    Product Preview DS21Q55 195 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: ESIBCR2 R egister Description: Extended System Information Bus Control Register 2 Register Address: B1h Bit # 7 6 5 4 3 2 1 0 Name - ESI4SEL2 ESI4SEL1 ESI4SEL0 - ESI3SEL2 ESI3SEL1 ESI3SEL ...

  • Maxim DS21Q55 - page 196

    Product Preview DS21Q55 196 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Register Name: ESIB1 Register Description: Extended System Information Bus Register 1 Register Address: B2h Bit # 7 6 5 4 3 2 1 0 Name DISn DISn DISn DISn DISn DISn DISn DISn Default 0 0 0 0 0 0 0 0 Bit ...

  • Maxim DS21Q55 - page 197

    Product Preview DS21Q55 197 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 29. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS21Q55 contains an on - chip clock synthesizer that generates a user - selectable clock referenced to the recovered receive clock (RCLK). The synthesize ...

  • Maxim DS21Q55 - page 198

    Product Preview DS21Q55 198 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 30. FRACTIONAL T1/E1 SUPPORT The DS21Q55 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in frac ...

  • Maxim DS21Q55 - page 199

    Product Preview DS21Q55 199 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 31. JTAG - BOUNDARY - SCAN ARCHITECTURE AND TEST - ACCESS PORT The DS21Q55 is an MCM consisting of 4 DS2155s. Each device has its on JTAG state machine and therefore is treated as 4 separate devices wh ...

  • Maxim DS21Q55 - page 200

    Product Preview DS21Q55 200 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TAP Controller State Machine The TAP controller is a finite state machine t hat responds to the logic level at JTMS on the rising edge of JTCLK (Figure 34 - 2) . Test - Logic - Reset Upon power - up, th ...

  • Maxim DS21Q55 - page 201

    Product Preview DS21Q55 201 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . Select - IR - Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the c ...

  • Maxim DS21Q55 - page 202

    Product Preview DS21Q55 202 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TAP CONTROLLER STATE DIAGRAM Figure 34 - 2 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 Select DR-Scan Capture DR Shift DR Exit DR Pause DR Exit2 DR Update DR Select IR-Scan Capture IR ...

  • Maxim DS21Q55 - page 203

    Product Preview DS21Q55 203 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 31.1 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the shift - IR state, the instru ...

  • Maxim DS21Q55 - page 204

    Product Preview DS21Q55 204 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . SAMPLE/P RELOAD This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfe ...

  • Maxim DS21Q55 - page 205

    Product Preview DS21Q55 205 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . DS21552 0002h 31.2 Test Registers IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional test register has been included with the DS2155 de ...

  • Maxim DS21Q55 - page 206

    Product Preview DS21Q55 206 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . BOUNDARY SCAN CONTROL BITS Table 34 - 4 NXA = Not Externally Available BIT PIN SYMBOL TYPE CONTROL BIT DESCRIPTION 2 1 RCHBLK O 2 JTMS I 1 3 BPCLK O 4 JTCLK I 5 JTRST I 0 6 RCL (NXA) O 7 JTDI I 77 8 UOP ...

  • Maxim DS21Q55 - page 207

    Product Preview DS21Q55 207 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . BIT PIN SYMBOL TYPE CONTROL BIT DESCRIPTION 53 48 TSIG I 52 49 TESO (NXA) O 51 50 TDATA (NXA) I 50 51 TSYSCLK I 49 52 TSSYNC I 48 53 TCHCLK O 47 - ESIBS1.cntl - 0 = ESIBS1 is an input; 1 = ESIBS1 is an ...

  • Maxim DS21Q55 - page 208

    Product Preview DS21Q55 208 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . BIT PIN SYMBOL TYPE CONTROL BIT DESCRIPTION 7 97 RFSYNC O 6 – RSYNC.cntl – 0 = RSYNC is an input; 1 = RSYNC is an output 5 98 RSYNC I/O 4 99 RLOS/LOTC O 3 100 RSYSCLK I 32. FUNCTIONAL TIMING DIAGRAM ...

  • Maxim DS21Q55 - page 209

    Product Preview DS21Q55 209 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE SIDE ESF TIMING Figure 35 - 2 NOTES: 1) RSYNC in frame mode (IOCR1.4 = 0) and double wide frame sync is not enabled (IOCR1.6 = 0). 2) RSYNC in frame mode (IOCR1.4 = 0) and double wide frame sync ...

  • Maxim DS21Q55 - page 210

    Product Preview DS21Q55 210 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35 - 3 NOTES: 1) RCHBLK is programmed to block channel 24. 2) Shown is RLINK/RLCLK in the ESF framing mode. CHANNEL 23 CHANNEL 24 CHANNE ...

  • Maxim DS21Q55 - page 211

    Product Preview DS21Q55 211 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE SIDE 1.544MHz BOUNDARY TIMI NG (With Elastic Store Enabled ) Figure 35 - 4 NOTES: 1) RSYNC is in the output mode (IOCR1.4 = 0). 2) RSYNC is in the input mode (IOCR1.4 = 1). 3) RCHBLK is programm ...

  • Maxim DS21Q55 - page 212

    Product Preview DS21Q55 212 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled) Figur e 35 - 5 NOTES: 1) RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one. 2) RSYNC is in the output mode (IOCR1 ...

  • Maxim DS21Q55 - page 213

    Product Preview DS21Q55 213 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE D4 TIMING Figure 35 - 6 NOTES: 1) TSYNC in the frame mode (IOCR1.2 = 0) and double - wide frame sync is not enabled (IOCR1.1 = 0). 2) TSYNC in the frame mode (IOCR1.2 = 0) and double - wid ...

  • Maxim DS21Q55 - page 214

    Product Preview DS21Q55 214 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE ESF TIMING Figure 35 - 7 NOTES: 1) TSYNC in frame mode (IOCR1.2 = 0) and double - wide frame sync is not enabled (IOCR1.3 = 0). 2) TSYNC in frame mode (IOCR1.2 = 0) and double - wide frame ...

  • Maxim DS21Q55 - page 215

    Product Preview DS21Q55 215 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35 - 8 NOTES: 1) TSYNC is in the output mode (IOCR1.1 = 1). 2) TSYNC is in the input mode (IOCR1.1 = 0). 3) TCHBLK is programmed to blo ...

  • Maxim DS21Q55 - page 216

    Product Preview DS21Q55 216 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled) Figure 35 - 9 NOTE: 1) TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG will be igno ...

  • Maxim DS21Q55 - page 217

    Product Preview DS21Q55 217 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled) Figure 35 - 11 NOTES: 1) TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored. 2) TCHBLK is programmed to block channel 31 ...

  • Maxim DS21Q55 - page 218

    Product Preview DS21Q55 218 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 32.2 E1 Mode RECEIVE SIDE TIMING Figure 35 - 11 NOTES: 1) RSYNC in frame mode (IOCR1.5 = 0). 2) RSYNC in multiframe mode (IOCR1.5 = 1). 3) RL CLK is programmed to output just the Sa bits. 4) RLINK will ...

  • Maxim DS21Q55 - page 219

    Product Preview DS21Q55 219 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled) Fi gure 35 - 12 NOTES: 1) RCHBLK is programmed to block channel 1. 2) RLCLK is programmed to mark the Sa4 bit in RLINK. 3) Shown is a RNAF fram ...

  • Maxim DS21Q55 - page 220

    Product Preview DS21Q55 220 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE SIDE BOUNDARY TIMING, R SYSCLK = 1.544MHz (With Elastic Store Enabled) Figure 35 - 13 NOTES: 1) Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link i ...

  • Maxim DS21Q55 - page 221

    Product Preview DS21Q55 221 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE SIDE BOUNDARY TIMING, RSYSCLK = 2.048MHz (With Elastic Store Enabled) Figure 35 - 14 NOTES: 1) RSYNC is in the output m ode (IOCR1.4 = 0). 2) RSYNC is in the input mode (IOCR1.4 = 1). 3) RCHBLK ...

  • Maxim DS21Q55 - page 222

    Product Preview DS21Q55 222 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE IBO CHANNEL INTERLEAVE MODE TIMING Figure 35 - 15 NOTES: 1) 4. 096MHz bus configuration. 2) 8.192MHz bus configuration. 3) 16.384MHz bus configuration. 4) RSYNC is in the input mode (IOCR1.4 = 0 ...

  • Maxim DS21Q55 - page 223

    Product Preview DS21Q55 223 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE IBO FRAME INTERLEAVE MODE TIMING Figure 35 - 16 NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 3) 16.384M Hz bus configuration 4) RSYNC is in the input mode (IOCR1.4 = 0). ...

  • Maxim DS21Q55 - page 224

    Product Preview DS21Q55 224 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . G.802 TIMING, E1 MODE ONLY Figure 35 - 17 NOTE: 1) RCHBLK or TCHBLK programmed to pulse high during timeslots 1 through 15, 17 through 25, and bit 1 of timeslot 26. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 ...

  • Maxim DS21Q55 - page 225

    Product Preview DS21Q55 225 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE TIMING Fig ure 35 - 18 NOTES: 1) TSYNC in frame mode (IOCR1.2 = 0). 2) TSYNC in multiframe mode (IOCR1.2 = 1). 3) TLINK is programmed to source just the Sa4 bit. 4) This diagram assumes bo ...

  • Maxim DS21Q55 - page 226

    Product Preview DS21Q55 226 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35 - 19 NOTES: 1) TSYNC is in the output mode (IOCR1.1 = 1.) 2) TSYNC is in the input mode (IOCR1.1 = 0). 3) TCHBLK is programmed to bl ...

  • Maxim DS21Q55 - page 227

    Product Preview DS21Q55 227 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE BOUNDARY TIMING, TSYSCLK = 1.544MHz (With Elas tic Store Enabled) Figure 35 - 20 NOTES: 1) The F - bit position in the TSER data is ignored. 2) TCHBLK is programmed to block channel 24. LS ...

  • Maxim DS21Q55 - page 228

    Product Preview DS21Q55 228 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE BOUNDARY TIMING, TSYSCLK = 2.048MHz (With Elastic Store Enabled) Figure 35 - 21 NOTE: 1) TCHBLK is programme d to block channel 31. LSB F LSB MSB CHANNEL 1 CHANNEL 32 AB C D A B TSYSCLK TS ...

  • Maxim DS21Q55 - page 229

    Product Preview DS21Q55 229 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT IBO CHANNEL INTERLEAVE MODE TIMING Figure 35 - 22 NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 3) 16.384MHz bus configuration 4) TSYNC is in input mode TSER LSB TSYSCLK ...

  • Maxim DS21Q55 - page 230

    Product Preview DS21Q55 230 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT IBO FRAME INTERLEAVE MODE TIMING Figure 35 - 23 NOTES: 1) 4.096MHz bus configuration. 2) 8.192MHz bus configuration. 3) 16.384MHz bus configuration 4) TSYNC is in input mode TSER LSB TSYSCLK TS ...

  • Maxim DS21Q55 - page 231

    Product Preview DS21Q55 231 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 33. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground - 1.0V to +6.0V Operating Temperature Range for DS21Q55 0 ° C to +70 ° C Operating Temperature Range for ...

  • Maxim DS21Q55 - page 232

    Product Preview DS21Q55 232 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECOMMENDED DC OPERATING CONDITIONS (0 ° C to +70 ° C for DS21Q55; - 40 ° C to +85 ° C for DS21Q55N) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 V IH 2.0 5.5 V Logic 0 V IL - 0.3 +0.8 V Supply ...

  • Maxim DS21Q55 - page 233

    Product Preview DS21Q55 233 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 34. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals, 20pF for all others. 34.1 Multipexed Bus AC Characteristics AC CHARACTERISTICS – MULTIPLEXED PARALLEL PORT (MUX = ...

  • Maxim DS21Q55 - page 234

    Product Preview DS21Q55 234 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . INTEL BUS READ TIMING (BTS = 0 / MUX = 1) Figure 37 - 1 INTEL BUS WRITE TIMING (BTS = 0 / MUX = 1) Figure 37 - 2 ASH PW t CYC t ASD t ASD PW PW EH EL t t t t t t AHL CH CS ASL ASED CS* AD0-AD7 DHR t DDR ...

  • Maxim DS21Q55 - page 235

    Product Preview DS21Q55 235 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . MOTOROLA BUS TIMING (BTS = 1 / MUX = 1) Figure 37 - 3 t ASD ASH PW t t ASL AHL t CS t ASL t t t DSW DHW t CH t t t DDR DHR RWH t ASED PW EH t RWS AHL PW EL t CYC AS DS AD0-AD7 (write) AD0-AD7 (read) R/W ...

  • Maxim DS21Q55 - page 236

    Product Preview DS21Q55 236 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 34.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS – NONMULTIPLEXED PARALLEL PORT (MUX = 0) (0 ° C to +70 ° C; V DD = 3.3V ± 5% for DS21Q55; - 40 ° C to +85 ° C; V DD = 3.3V ± 5% for ...

  • Maxim DS21Q55 - page 237

    Product Preview DS21Q55 237 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . INTEL BUS READ TIMING (BTS = 0 / MUX = 0) Figure 37 - 4 INTEL BUS WRITE TIMING (BTS = 0 / MUX = 0) Figure 37 - 5 Address Valid Data Valid A0 to A7 D0 to D7 WR* CS* RD* 0ns min. 0ns min. 75ns max. 0ns mi ...

  • Maxim DS21Q55 - page 238

    Product Preview DS21Q55 238 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . MOTOROLA BUS READ TIMING (BTS = 1 / MUX = 0) Figure 37 - 6 MOTOROLA BUS WRITE TIMING (BTS = 1 / MUX = 0) Figure 37 - 7 Address Valid Data Valid A0 to A7 D0 to D7 R/W* CS* DS* 0ns min. 0ns min. 75ns max. ...

  • Maxim DS21Q55 - page 239

    Product Preview DS21Q55 239 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 34.3 Receive Side AC Characteristics AC CHARACTERISTICS – RECEIVE SIDE (0 ° C to +70 ° C; V DD = 3.3V ± 5% for DS21Q55; - 40 ° C to +85 ° C; V DD = 3.3V ± 5% for DS21Q55N) PARAMETER SYMBOL MIN T ...

  • Maxim DS21Q55 - page 240

    Product Preview DS21Q55 240 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . NOTES: 1) Jitter attenuator enabled in the receive path. 2) Jitter attenuator disabled or enabled in the transmit path. 3) RSYSCLK = 1.544MHz. 4) RSYSCLK = 2.048MHz. 5) RSYSCLK = 4.096MHz. 6) RSYSCLK = ...

  • Maxim DS21Q55 - page 241

    Product Preview DS21Q55 241 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE SIDE TIMING, ELASTIC STORE ENABLED (T1 MODE) Figure 37 - 9 NOTES: 1) RSYNC is in the output mode. 2) RSYNC is in the input mode. 3) F - bit when CCR1.3 = 0, MSB of TS0 when CCR1.3 = 1. F t t R t ...

  • Maxim DS21Q55 - page 242

    Product Preview DS21Q55 242 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . RECEIVE LINE INTERFACE TIMI NG Figure 37 - 10 t F t R RPOSI, RNEGI RCLKI CL t t CP CH t t SU t HD t DD RPOSO, RNEGO RCLKO LL t t LP LH t ...

  • Maxim DS21Q55 - page 243

    Product Preview DS21Q55 243 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 34.4 Transmit AC Characteristics AC CHARACTERISTICS – TRANSMIT SIDE (0 ° C to +70 ° C; V DD = 3.3V ± 5% for DS21Q55; - 40 ° C to +85 ° C; V DD = 3.3V ± 5% for DS21Q55N) PARAMETER SYMBOL MIN TYP ...

  • Maxim DS21Q55 - page 244

    Product Preview DS21Q55 244 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 4) TSYSCLK = 8.192MHz. 5) TSYSCLK = 16.384MHz TRANSMIT SIDE TIMING Figure 37 - 11 4) TCHCLK and TCHBLK are synchronous with TCLK when the transmit - side elastic store is disabled. NOTES: 1) TSYNC is in ...

  • Maxim DS21Q55 - page 245

    Product Preview DS21Q55 245 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT SIDE TIMING, EL ASTIC STORE ENABLED Figure 37 - 12 t F t R TSYSCLK TSER TCHCLK t t SL t SH SP TSSYNC TCHBLK t D3 t D3 t t t SU HD SU t HD NOTES: 1) TSER is only sampled on the falling edge of T ...

  • Maxim DS21Q55 - page 246

    Product Preview DS21Q55 246 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . TRANSMIT LINE INTERFACE TIMING Figure 37 - 13 TCLKO TPOSO, TNEGO t DD t F t R TCLKI TPOSI, TNEGI t t LL t LH LP t HD t SU ...

  • Maxim DS21Q55 - page 247

    Product Preview DS21Q55 247 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . 35. MECHANICAL DESCRIPTIONS ...

  • Maxim DS21Q55 - page 248

    Product Preview DS21Q55 248 of 248 0121 03 Please contact telecom.support@dalsemi.com or search http://www.maxim - ic.com for updated information . ...

Manufacturer Maxim Category Marine Radio

Documents that we receive from a manufacturer of a Maxim DS21Q55 can be divided into several groups. They are, among others:
- Maxim technical drawings
- DS21Q55 manuals
- Maxim product data sheets
- information booklets
- or energy labels Maxim DS21Q55
All of them are important, but the most important information from the point of view of use of the device are in the user manual Maxim DS21Q55.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Maxim DS21Q55, service manual, brief instructions and user manuals Maxim DS21Q55. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Maxim DS21Q55.

Similar manuals

A complete manual for the device Maxim DS21Q55, how should it look like?
A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Maxim DS21Q55 by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Maxim DS21Q55.

A complete Maxim manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

1. Preface and tips on how to use the manual Maxim DS21Q55 - At the beginning of each manual we should find clues about how to use the guidelines. It should include information about the location of the Contents of the Maxim DS21Q55, FAQ or common problems, i.e. places that are most often searched by users in each manual
2. Contents - index of all tips concerning the Maxim DS21Q55, that we can find in the current document
3. Tips how to use the basic functions of the device Maxim DS21Q55 - which should help us in our first steps of using Maxim DS21Q55
4. Troubleshooting - systematic sequence of activities that will help us diagnose and subsequently solve the most important problems with Maxim DS21Q55
5. FAQ - Frequently Asked Questions
6. Contact detailsInformation about where to look for contact to the manufacturer/service of Maxim DS21Q55 in a specific country, if it was not possible to solve the problem on our own.

Do you have a question concerning Maxim DS21Q55?

Use the form below

If you did not solve your problem by using a manual Maxim DS21Q55, ask a question using the form below. If a user had a similar problem with Maxim DS21Q55 it is likely that he will want to share the way to solve it.

Copy the text from the picture

Captcha
New picture

Comments (0)