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Manual Cypress CYD02S36VA

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  • Cypress CYD02S36VA - page 1

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V FLEx36™ 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-06076 Rev . *G Revised Decenber 09, 2008 Features ■ T rue dual-ported memory cells that enable simul ...

  • Cypress CYD02S36VA - page 2

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 2 of 28 Logic Block Diagram [1] FTSEL L PORTSTD[1: 0] L DQ [35:0] L BE [3:0] L CE 0 L CE1 L OE L R/W L FTSEL R PORTSTD[1:0] R DQ [35:0] R BE [3:0] R CE 0 R CE1 R OE R R/W R A [18:0] L CNT/MSK L ADS L CNTEN L CNTRST L RET L CNTINT L C L WRP L A [18:0] R C ...

  • Cypress CYD02S36VA - page 3

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 3 of 28 Pin Configurations Figure 1. Pin Diagram - 256-Ball FBGA (T op View) CYD01S36V/CYD02S36V/36V A/CYD04S36V/CYD09S36V/CYD18 S36V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A DQ32L DQ30L DQ28L DQ26L DQ24L DQ22L DQ20L DQ18L DQ 18R DQ20R DQ22R DQ24R DQ26R ...

  • Cypress CYD02S36VA - page 4

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 4 of 28 Pin Definitions Left Port Right Port Description A 0L –A 18L A 0R –A 18R Address In puts . BE 0L –BE 3L BE 0R –BE 3R Byte Enable Input s . Asserting these signals ena bles Read and Write operations to the corresponding bytes of the memory ...

  • Cypress CYD02S36VA - page 5

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 5 of 28 Master Reset The FLEx36 family devices un dergo a complete reset by taking its MRST input LOW . The MRST input can switch asynchro- nously to the clocks. An MRST initializes the inte rnal burst counters to zero, and the coun ter mask registers to ...

  • Cypress CYD02S36VA - page 6

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 6 of 28 Counter enable (CNTEN ) inputs are provided to stall the operation of the address input and use the internal addre ss generated by the intern al counter for fast, interleaved me mory applications. A port’s burst counter is loade d when the port ...

  • Cypress CYD02S36VA - page 7

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 7 of 28 Counter Increment Operat ion Once the address counter registe r is initially loaded with an external address, the counter can internally increment the address value, potentiall y addr essi ng the entire memo ry array . Only the unmasked bits of t ...

  • Cypress CYD02S36VA - page 8

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 8 of 28 From Mask Register Mirror Coun ter Address Decode RAM Array Wra p 1 0 Increment Logic 1 0 +1 +2 1 0 Wra p Detect From Mask From Counter To Counter Bit 0 Wra p Figure 2. Counter , Mask, a nd Mirror Logic Block Di agram [1] 17 17 17 17 17 1 0 Load ...

  • Cypress CYD02S36VA - page 9

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 9 of 28 IEEE 1 149.1 Serial Boundary Scan (JT AG) [23] The FLEx36 fami ly devices incorporate an IEEE 1 149 .1 serial boundary scan test access port (T AP). The T AP controller functions in a manner that does no t conflict with the operation of other dev ...

  • Cypress CYD02S36VA - page 10

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 10 of 28 D2 TDI TDO TDO TDI D1 TDO TDI D4 TDO TDI D3 TDO TDI Figure 4. Scan Chain for 18-Mbit Device D2 TDO TDI D1 TDO TDI TDI TDO Figure 5. Scan Chain for 9-Mbit Device T able 4. Identification Register Definitions Instruction Field Va l u e Desc riptio ...

  • Cypress CYD02S36VA - page 11

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 1 1 of 28 T able 6. Instruction Identificatio n Codes Instruct ion Code Description EXTEST 0000 Captures the Input/Ou tput ring contents. Places the BSR between the TDI and TDO. BYP ASS 1 1 1 1 Places the BYR between TDI and TDO. IDCODE 101 1 Loa ds the ...

  • Cypress CYD02S36VA - page 12

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 12 of 28 Maximum Ratin gs Exceeding maximum ratings [25] may shorten the useful life of the device. User gui delines are no t tested. S torage T emperature ................. .............. ... –65°C to +150°C Ambient T emperature with Power Applied . ...

  • Cypress CYD02S36VA - page 13

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 13 of 28 Figure 6. AC T est Load and Waveforms Switching Characteristics Over the Operating Range Parameter Description -167 -133 -100 Unit CYD01S36V CYD02S36V/ CYD02S36V A CYD04S36V CYD09S36V CYD01S36V CYD02S36V CYD04S36V CYD09S36V CYD18S36V CYD18S36V M ...

  • Cypress CYD02S36VA - page 14

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 14 of 28 t HCM CNT/MSK Hold T ime 0.6 0.6 NA NA ns t OE Output Enable to Data V alid 4.4 4.4 5.5 5.5 ns t OLZ [31, 32] OE to Low Z 0 0 0 0 ns t OHZ [31, 32] OE to High Z 0 4.0 0 4.4 0 5.5 0 5.5 ns t CD2 Clock to Data V alid 4.4 4.4 5.0 5.2 ns t CA2 Clock ...

  • Cypress CYD02S36VA - page 15

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 15 of 28 JT AG Switching W aveform T est Clock T est Mode Select TCK TMS T est Data-In TDI Te s t D a t a - O u t TDO t TCYC t TMSH t TL t TH t TMSS t TDIS t TDIH t TDOX t TDOV Switching W aveforms Figure 7. Master Reset MRST t RSR t RS INACTIVE ACTIVE T ...

  • Cypress CYD02S36VA - page 16

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 16 of 28 Figure 8. Read Cycle [14, 33, 34, 35, 36] Notes 33. OE is asynchronously controlled; all other inputs (excluding MRST and JT AG) are synchronous to the rising clock edge. 34. ADS = CNTEN = LOW , and MRST = CNTRST = CNT/MSK = HIGH. 35. The output ...

  • Cypress CYD02S36VA - page 17

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 17 of 28 Figure 9. Bank Select Re ad [37, 38] Figure 10. Read-to -Write-to-Read (OE = LO W) [36, 39, 40, 41, 42] Notes 37. In this depth-expansion exa mple, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx36 device fr om th ...

  • Cypress CYD02S36VA - page 18

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 18 of 28 Figure 1 1. Read-to-Write-to-Read (OE Controlled) [36, 39, 41 , 42] Figure 12. Read with Address Counter Advance [41] Switching W aveforms (continued ) t CYC2 t CL2 t CH2 t HC t SC t HW t SW t HA t SA A n A n+1 A n+2 A n+3 A n+4 A n+5 t HW t SW ...

  • Cypress CYD02S36VA - page 19

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 19 of 28 Figure 13. Write with Address Counter Advance [42] Switching W aveforms (continued ) t CH2 t CL2 t CYC2 A n A n+1 A n+2 A n+3 A n+4 D n+1 D n+1 D n+2 D n+3 D n+4 A n D n t SAD t HAD t SCN t HCN t SD t HD WRITE EXTERNAL WRITE WITH COUNTER ADDRESS ...

  • Cypress CYD02S36VA - page 20

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 20 of 28 Figure 14. Counter Reset [4 3, 44] Notes 43. CE 0 = BE0 – BE3 = L OW; CE 1 = MRS T = CNT/MSK = HIGH. 44. No dead cycle exists during counter reset. A Read or W rite cycle may be coincident al with the counter reset. 45. Retransmit happens if t ...

  • Cypress CYD02S36VA - page 21

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 21 of 28 Figure 15. Readback St ate of Address Counter or Mask Reg ister [46, 47, 48 , 49] Notes 46. CE 0 = OE = BE 0 – BE3 = LOW; CE 1 = R/W = CNTRST = MRST = HIGH. 47. Address in output mode. Host must not be driving address bus af ter t CKLZ in next ...

  • Cypress CYD02S36VA - page 22

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 22 of 28 Figure 16. Lef t_Port (L_Port) W r ite to Right_Port (R_Port) Read [50, 51, 52 ] Notes 50. CE 0 = OE = ADS = CNTEN = BE0 – BE 3 = LOW; CE 1 = CNTRST = MRST = CNT/MSK = HIGH. 51. This timing is valid when one port is writing, and ot her port is ...

  • Cypress CYD02S36VA - page 23

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 23 of 28 Figure 17. Counter Inter rupt and Retransmit [17, 45, 53, 54, 55, 56] Notes 53. CE 0 = OE = BE 0 – BE3 = LOW; CE 1 = R/W = CNTRST = MRST = HIGH. 54. CNTINT is always driven. 55. CNTINT goes LOW when the unmasked port ion of the address counter ...

  • Cypress CYD02S36VA - page 24

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 24 of 28 Figure 18. MailBox In terrupt T iming [57, 58, 59, 60, 61] Switching W aveforms (continued ) t CH2 t CL2 t CYC2 CLK L t CH2 t CL2 t CYC2 CLK R 7FFFF t SA t HA A n+3 A n A n+1 A n+2 L_PORT ADDRESS A m A m+4 A m+1 7FFFF A m+3 R_PORT ADDRESS INT R ...

  • Cypress CYD02S36VA - page 25

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 25 of 28 Ordering Information 512K × 36 (18-Mbit) 3.3V Synchro nous CYD18S36V Dual-Port SRAM Speed( MHz) Ordering Code Package Name Package T ype Operating Range 133 CYD18S36V - 133BBC BB256B 256-ball Grid Arr ay 23 mm × 23 mm with 1.0-mm pitch (BGA) C ...

  • Cypress CYD02S36VA - page 26

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 26 of 28 Package Diagrams BOTTOM VIEW TOP VIEW 1 0 987654 32 1 A B C D E F G H J K PIN 1 CORNER PIN 1 CORNER 0.20(4X) Ø 0 . 2 5MCAB Ø0.05 M C Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K) 0.25 C 0.70±0.05 C SEATING PLANE 0.15 C 16 15 14 13 12 11 T R ...

  • Cypress CYD02S36VA - page 27

    CYD01S36V CYD02S36V/36V A/CYD04S36V CYD09S36V/CYD18S36V Document Number: 38-06076 Rev . *G Page 27 of 28 Package Diagrams (continued) TOP VIEW 15.00 1.00 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K PIN 1 CORNER PIN 1 CORNER 0.20(4X) Ø0.25 M C A B Ø0.05 M C 0.25 C 0.70±0.05 C SEATING PLANE 0.15 C 0.35 16 15 14 13 12 11 T R P M N L N T R P M L K J F ...

  • Cypress CYD02S36VA - page 28

    Document Number: 38-06076 Rev . *G Revised Decenber 09, 2008 Page 28 of 28 FLEx36 and FLEx3 6-E are tradem arks of Cypress Se miconductor Corporation. All other t rademarks or reg istered trad emarks referen c ed herein a re property o f the respec tive corporat ions. All prod ucts and compan y names mentioned in this documen t may be the trad emar ...

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All of them are important, but the most important information from the point of view of use of the device are in the user manual Cypress CYD02S36VA.

A group of documents referred to as user manuals is also divided into more specific types, such as: Installation manuals Cypress CYD02S36VA, service manual, brief instructions and user manuals Cypress CYD02S36VA. Depending on your needs, you should look for the document you need. In our website you can view the most popular manual of the product Cypress CYD02S36VA.

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A manual, also referred to as a user manual, or simply "instructions" is a technical document designed to assist in the use Cypress CYD02S36VA by users. Manuals are usually written by a technical writer, but in a language understandable to all users of Cypress CYD02S36VA.

A complete Cypress manual, should contain several basic components. Some of them are less important, such as: cover / title page or copyright page. However, the remaining part should provide us with information that is important from the point of view of the user.

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